LPDDR4 memories

[joniengr081]

Hi,

I am wondering about the LPDDR4 memories that can be used with ZYNQ Ultrascale devices. I have some questions. I am referring to the memories by Micron Technology. 

1- What is the signal rank and dual rank in the memories ?
2- What is the single die package (SDP) and dual die package (DDP) ?

[Daixiwen]

In a dual die package, as the name suggest you have two silicon dies in the same package. It means that your memory is divided in two and each die can be individually selected with a chip select. Your DDR memory controller will probably see this as two chips connected to the same bus.

[joniengr081]

Thanks for the reply. I guess the dual memory chip will also help in routing on the custom board compared to two chips as all the data and address has to go to only one chip not two. But what is the word "rank", signal rank and dual rank are the same as single die and dual die ?

[Daixiwen]

As far as I understand it, it is the same.

[joniengr081]

I have checked some Xilinx documents describing memory interfaces to Ultrascale FPGA/SOC devices. One single rank configuration can be achieved with using one SDP memory which can also be called single channels single rank configuration using SDP. While two single rank can be implemented with one DDP which can also be called dual channel single rank configuration using DDP. It look like that single rank and dual rank are not the same as single die per package (SDP) and dual die per package (DDP).

[ejeffrey]

'rank' is the number of chip selects that the controller uses to address the memory.  You can have dual rank either by using chips with multiple chip select lines, or having two sets of chips.

[joniengr081]

Yes, now I also get it that rank actually is chip select. We can implement dual rank by having two single die package (SDP) or using one dual die package (DDP). All the data line, address lines, control and configuration are shared in dual rank configuration, meaning same set of signals or connections between memory and memory controller. For example, if the memory interface is 32 bit data, then these data lines will be connected to each rank in dual rank configuration. The question is what is the gain by having data sorted at two different physical memories in dual rank configuration. If the data has to be the same in dual rank then what is the gain ?

[Daixiwen]

The point is to have more memory in the same package. You use the chip selects to enable only one rank at a time, you can't use both at the same time. Function wise you must see this as an extra address bit, not a doubled data width. As it is sometimes cheaper to put two smaller dies in the same package than having a big die, it is an option that can be economically viable in some cases. The controller must just be configured to use the extra chip select signal.

[joniengr081]

Alright, now it is clear if we select one rank at a time with chip select. Then the gain is routing in dual rank with slower access rate compared to to channel single rank ? As we need to route the same set of signals including data lines, address lines, control and configuration lines between memory controller and both chips in dual rank. This can be two die in one package, DDP. To be clear here, then both chips will be in series to the memory controller, meaning that the same set of signals will be further router to the second chip, right ? As chips can be selected one at a time, which is seen like an additional address bit by the memory controller.

To get the same storage as single channel dual rank, we need to have two channels with single rank in which each memory will have parallel connection to the memory controller, like channel A and channel B. in each channel there will be complete set of data lines, address lines, control lines, and configuration lines. Each set will be routed between memory controller and the memory chips. This way we can have faster access but the trouble will be in routing two set of signals.

[Daixiwen]

In a DDP both dies are connected in parallel inside the chip. So you route one set of signals form the controller to the chip, and the controller will see this as two chips connected to the same bus.

When you use two separate single die chips, you can connect them in different ways. You can connect in parallel both the control/address bus and the data bus, and use the chip select as with the DDP chip. You can also have independent channels, routing separate control/address and data busses from the controller to both chips (if the controller supports it). Then both chips can be accessed simultaneously, at different addresses. Or you can also connect them on a wider data bus: you connect the control/address bus in parallel to both chips, but have separate data busses from the controller to each chip. The controller will then see this as a single rank, but with a wider data bus, increasing the bandwidth.

The documentation for your LPDDR controller probably lists those different schemes and which ones are supported.

[joniengr081]

If both dies in DDP are connected internally in parallel for their data, address and control lines, then I think DDP package can only used in dual rank configuration in which memory can controller select one die at a time, right ?

[Daixiwen]

Yes that's right. The other schemes can only be used with separate chips