I slowly moved from Verilog into SV around the time I started working with AXI bus a lot, and so connecting 40+ signals every time wasn't much fun, SV's interface made this painless as just one connection is required for entire bus. That was too good of a feature to pass by. And now I use interfaces in just about any of my modules, except for some very simple ones. Add some other creature comfort features like not having to type a signal name twice while connecting a module if signal name is the same as port name, and you have a winner.
I did study both VHDL and Verilog in University (SV wasn't a thing yet when I was there), but chose Verilog every time I had a choice (obviously had to use VHDL during VHDL labs). VDHL code tend to have too low of an SNR for my taste.
But... just you wait for resident VDHLers to show up in force over here, and tell you how bad SV is, even though most of them know jack shit about it