Anyone use Altera Quartus II software and Cyclone II FPGA?

[Robo_Pi]

UPDATE:

Instead of starting a whole new thread, I thought I'd ask another question on the Altera Quartus II software.

By the way, I've downloaded and I'm reading through the Free Range VHDL book.   It is a pretty nice introduction to the topic, and it's a free download too.

Anywhere where I'm at now is that I have created two projects using Quartus II.   One is just a simple 3-bit binary counter.   It actually just counts from 0 to 7 in binary using the onboard LEDs on the Cyclone II mini development board.  The second project is a block diagram schematic created using 3 of the maxplus2 74595 shift registers.    I just did this for educational purposes to see if I could replace 3 shift regs on a breadboard with this FPGA board.
 
Both projects work just fine on their own.  They also don't have any IO pin conflicts.   So now I would like to compile both of these projects as a single project.  I've created the new project that contains both the VHDL binary counter file, and the LED Panel *.bdf file.   The problem is that I can only set one of these to be the "Top-Level Entity".   So it only wants to compile one or the other, but not both at the same time.

So my question is:

How do I combine these two files into a single "Top-Level Entity"?   Or to be more precise how do I have Quartus II compile the whole shebang?

Is there a way to "include" files in a compilation without having to set them all to "Top-Level Entity" which doesn't seem to be possible?

Can I just "include" the LED_Panel.bdf file in the VHDL code somehow for the 3-bit_counter.vhd?  I'm not aware of any "include" statements for the VHLD.

Do I need to somehow "tie" these two circuits together so it thinks they are part of a single larger circuit?

I just don't know how to get these to both be programmed into the FPGA simultaneously.  It seems to want to only do one or the other depending on which is set to "Top-Level Entity".

Anyone know how to do this?

Thanks.

[mac.6]

You need to create a toplevel that instantiate both design.
It's pretty much the "standard" way to do (never put IP into toplevel, or only if small). This way you can reuse them in another design.

[Robo_Pi]

You need to create a toplevel that instantiate both design.

With all due respect I pretty much guessed this much. 

Can anyone explain how this is done?

If I knew how to do that I would have done it already. 

Thank you.

[Siwastaja]

Create one "entity" per file. Entity has the list of ports, and the implemtation. It's your basic building block.

Then, you can use them as "components" in other entities. Any entity can be instantiated in any other entity, as many times you want.

Often, it makes sense to make a "top level" that only instantiates other entities, but does not implement a lot of its own actual logic. This is not required, just a cleanliness thing.

Many sources (such as https://www.doulos.com/knowhow/vhdl_designers_guide/components_and_port_maps/ ) teach you the "old way" that you need to declare a component first, then instantiate it separately - this is a lot of copy paste work where you need to reformat the text to look a bit different. Emacs text editor, for example, has automated copypaste functionality to copy a ENTITY declaration, then paste it as a component declaration.

Now just create one top-level entity - its port declaration will be the actual physical FPGA pins. Then set this entity as the top level entity, IIRC by second-clicking the file and doing the magic on that menu. Then compile the design, then you use the Quartus Pin Planner or constraint editor to actually map your top level entity port names (they can be anything, such as LED_OUT) to actual pin numbers (such as PIN_123 on a QFP package or PIN_AG67 on a BGA package).

Then instantiate other entities as components within that toplevel entity. Using all that copypaste magic. Then, for the connecting wires, you need to generate signals, then connect these signals to the PORT MAPS. So, some more copypasting.

Connecting blocks in VHDL is a lot of tedious copy paste work. A lot of more or less usable tools exist, trying to make this easier.

All this copypasting makes little sense. AFAIK, most if not all VHDL compilers support direct instantiation (VHDL-93 addition) of an entity without needing to first declare a component. For reference:
http://www.ics.uci.edu/~jmoorkan/vhdlref/compinst.html
This reduces the error-prone and ugly copypaste work somewhat.

VHDL is tedious to write and suffers from many historical brainfarts. Another example is the totally insane "sensitivity list" concept, which is just simply a concept of the programmer making a super-simple compiler optimization step for the compiler, manually writing a list of things the compiler only need to look at - this was to speed up simulation in 1980's! It's not a way to describe a design; but if you get it wrong, you get mismatch between simulation and real world! Modern compilers check this list and warn you if you have typed it wrong. It's still insane. Luckily, most of the time, we end up writing synchronous logic where the sensitivity list is limited to clk and reset, but this is even more a reason you need to be careful when writing that rare asynchronous process...

[bingo600]

I'm using that excact board w. Quartus II 13.0-sp1  (sp1 is important)

Running on Linux Mint 17.3 x64 (Same as ubuntu trusty)

I can recommend this selfstudy course for Altera

http://www.pyroelectro.com/edu/fpga/introduction/

Forum w. a lot of my homework for the course
http://www.pyroelectro.com/forums/viewforum.php?f=26&sid=aa2477f7be05bfe61b1aabdd43fe2d20




/Bingo

[james_s]

Have a look at this project: http://searle.hostei.com/grant/Multicomp/

It's based on the same board you're using, and it illustrates nicely how to combine several VHDL modules under a top level file.

[obiwanjacobi]

This is how I do it:

Code: [Select]

-- direct instantiation of MemoryDecoder entity
memoryDecoder: entity work.MemoryDecoder(MemoryDecoder_rtl)
port map (nMEMREQ=>n_memreq, MA=>ma, nMBE=>n_mbe);
Disclaimer: hobbyist.

[FlyingDutch]

Hello,

there is interesting project related to emulate few "retro computers" on your FPGA board. Here is link to it:

http://searle.hostei.com/grant/Multicomp/

But this stuff is for a bit most experienced user of FPGA. But it is really good example how to project hardware on FPGAs and everybody can learn much from these examples 

Kind Regards