Anyone use Altera Quartus II software and Cyclone II FPGA?

[Robo_Pi]

Hi,

I'm totally new to FPGA design.  I've just downloaded Altrea's Quartus II version 11.1 software to program some Cyclone II FPGA boards I have.  I also have some Max II CPDLs.

The boards I have:

FPGA Altera Cyclone II EP2C5


CPLD Altera MAX II EPM240


I'm totally NEW to this so I have almost no clue what I'm doing.  I'm hoping to find other hobbyists who could help me learn, or perhaps we could learn together? 

So far I've installed the software and USB Blaster.  I've typed in a VHDL hardware description from a YouTube tutorial that uses the same software and the same board I have.

This is the YouTube tutorial I used.  I have this exact same board.

Everything went just fine.  I typed it all in, complied it, downloaded it onto the board, and it does exactly what it's supposed to do.  In fact, I even modified it some to do a few different things and to my utter shock and amazement even my modifications worked as expected.  So I'm off to a good start.

However, in spite of the great success up to this point I still have a lot of things I'm not understanding.   I was able to create a schematic file using the original VHDL code.   And then I wanted to modified the schematic, but I'm running into problems there when I tried to break out pins on a bus. 

I have a specific goal in mind that I would like to achieve.  Well, for one thing, I'd like to learn how to work with the Schematic diagram better.  I understand electronics and I've worked with many schematic programs in the past so it's not that I don't understand schematics.  For some reason I'm just not having any luck connecting individual pins to a bus.

My ultimate goal is to re-design this entire project using the schematic alone without typing in any VHDL.   The reason I want to do this is so I can work in schematic mode for a while to see if there are ways to reduce gate count in the design.   Then I can go back into the VHDL and see what I would need to do there to reproduce the schematics I created by hand.

In short, this entire project is just for leaning how to program the Cyclone II efficiently.   I'm not concerned with any actual finished product at this time.    What I would like to do is start a thread on this where I can post everything we're doing step-by-step for others to follow along and perhaps even suggest improvements.  But I can't do it alone since I'm not clear myself on exactly how to work with the software tools.

So the project right now is the following:

I have a 50 MHz clock.   This clock needs to be reduced to 1 Hz.   

The very first thing I would like to do is write a hardware schematic that achieves this reduction using the fewest possible logic gates.

Then learn how to write a VHDL description that will produce the same hardware using the same number of gates.

From there I would then move on to doing something similar with a binary counter.

This is all just for the purpose of learning VHDL and schematic design with a full understanding of precisely what's going on.

If possible, once the above has been achieved, I would then like to move on to seeing if the same thing could be designed using a Finite State Machine?  Again, just for the purpose of understanding how to use these design tools.

~~~~~~

My ultimate long term goal is to eventually program neural networks onto the FPGA.   But I don't want to jump into that until I've gained a really solid understanding of how to program the FPGA in general.  I'm also sure I'll be interested in using the FPGA to control PWM motors, as well as other projects.  But for now, I just want to start with this very basic project.  Reduce 50 MHz to 1Hz using the least number of gates, and fully understand it in both VHDL, schematic, and perhaps even as a Finite State Machine.

Big dreams.  But I want to start with very simple stuff until I feel confident with the tools.

Anyone interested in contributing to this project?

If we create a nice step-by-step thread it should be useful for a lot of people. 

Thanks for reading.

[jackbob]

I don't want to seem like I'm plugging this forum with my new video series but I do want to share it with others and help beginners get started with FPGA's (it was a steep learning curve for me years ago with limited resources).

It will take some time to complete but here is the playlist as of now.
https://www.youtube.com/playlist?list=PL7EPI_3oZX_wiq2NJBFJGvUD0dsnChRi9

With that said based on what you described if you truly want to understand the more fundamentals and are at a beginner level, then watch my video series I am currently producing. Its still very early in the making but is aimed for people in your exact position. I would recommend the Free Range VHDL book. I show this book within the first few minutes of my first video and highly recommend it for any beginner.

To address more of your exact details.  I strongly encourage you to stay away from the schematic editor for many reasons (this is the subject of my next video) but put simply its useless for designing any circuits of modest complexity and it teaches you nothing. Yes you can build a basic logic design fast and intuitive but anything beyond a basic design you might find in a first semester digital circuits class, the schematic editor is useless. It actually takes more time to build even simple circuits with the schematic editor than to describe them using a few lines of VHDL.

As for your hardware issues I didn't read through them in much detail but a few things I noticed already. Why are you using Quartus 11.1 and not Quartus Prime 17.1? Does your board have flash storage? I don't see any in the picture you linked (if you don't know what that is or why its needed, watch my first video). What exactly do you mean by break out pins to a bus? I'm not certain but perhaps my third video will address this problem if it is what I think you are trying to describe.

[BrianHG]

As for your hardware issues I didn't read through them in much detail but a few things I noticed already. Why are you using Quartus 11.1 and not Quartus Prime 17.1? Does your board have flash storage? I don't see any in the picture you linked (if you don't know what that is or why its needed, watch my first video). What exactly do you mean by break out pins to a bus? I'm not certain but perhaps my third video will address this problem if it is what I think you are trying to describe.

He has a cyclone II, He can only go up to Quartus 13.  Quartus 11 was the last version which has the built in simulator if I remember correctly.

[jackbob]

Oh I see, sorry I read somewhere in your post MAX II which is supported in 17.1. In the case of the cyclone II yes you are correct. The software is still similar and you will be able to follow regardless.

[Robo_Pi]

He has a cyclone II, He can only go up to Quartus 13.  Quartus 11 was the last version which has the built in simulator if I remember correctly.

That's correct.  I have five of these Cyclone II boards so I downloaded the software that is most compatible with them.   Also, since I'm just starting out I don't see this as being a limitation.  I can always move up to newer versions and chips later.   But as a beginner I should be able to do quite a bit with the Cyclone II.

By the way, I solved the bus breakout problem already.  Well, actually I don't even know how I solved it.  All I did was erase the original schematics and drew it over again from scratch and this time everything worked.

By the way, to jackbob.  It's important for me personally to work with the schematic level design in the beginning.   I'm fully aware that I'm not going to want to design extremely complex circuits using schematic design.   But that's not my purpose right now.  My purpose is to create very simple designs in both schematic and VHDL and exam which design is using logic gates most efficiently.   This is just something I need to understand and see for myself.   In the end, I believe this will actually help me write better VHDL even when I get to more complex projects.

So for me the circuit design level is something I want to do at the very beginning.   As you point out, it's not something that I'll even be able to do when things become more complex.  So this is where it needs to be done if I am ever going to get a feel for how VHDL relates to the hardware design.  Seeing the actual relationship at a very simple level is precisely my goal.

[jackbob]

My purpose is to create very simple designs in both schematic and VHDL and exam which design is using logic gates most efficiently.   This is just something I need to understand and see for myself.   In the end, I believe this will actually help me write better VHDL even when I get to more complex projects.

Are you trying to understand FPGA's or digital logic as a whole? The whole purpose of VHDL is to let the synthesizer do the heavy lifting for you (i.e.design and optimize your circuit). If you are trying to learn basic logic and avoid using 7400 logic and breadboards, then the schematic editor is best for that purpose. It will allow you to design circuits using schematics you are comfortable with without worrying about a whole other subject, that is VHDL. If you already understand basic digital logic and optimization such as K-maps and you are looking to to design meaningful systems, VHDL is the next step. At first I was tied to the schematic editor and did not understand why anyone would want to use a language to describe a circuit. I spent a while using the schematic editor and finally went for VHDL. After learning VHDL, I wish I had done so earlier. The power of abstraction is amazing and is something which cannot be achieved through the schematic editor. It is desirable to not think of designs on the gate level, this is so low level it takes ages to make any design. Let the synthesizer work on the gate level and you tell it how you want to optimize the circuit.

[jackbob]

In the end, I believe this will actually help me write better VHDL even when I get to more complex projects.

I don't want to come off as rude or condescending at all but...

No it won't.

Again if you are trying to understand digital logic then this is perfect! If you think this will help you write VHDL, you are misunderstanding the purpose VHDL.

[Robo_Pi]

Are you trying to understand FPGA's or digital logic as a whole?

Neither.   I already understand FPGAs.   They are simply chips that contain field programmable gate arrays.  So I already know what an FPGA is.  I also understand digital logic as a whole.  I've worked the digital logic chips on breadboards for decades.   So I understand schematics and digital logic.   

What I'm trying to get at is the efficiency of VHDL, or more precisely the question of how sloppy VHDL will allow a designer to be.

I have a burning question that I need to answer for myself.   And that question is as follows:

When I write the VHDL code to reduce a 50 Mhz clock to a 1 Hz signal I see that it requires 89 LEs to implement that on the FPGA chip.

So far so good.  It was EASY to write the VHDL code.  And the chip was programmed and is running.  I could just run out and have a beer and call it a day.  But I have this burning question of whether this task really requires 89 LEs, or whether it could have been done more efficiently had I actually sat down and figured out the most efficient possible logic circuit.  I can only do that using the schematic layout because that's what I'm good at. 

It may indeed be impossible to reduce this take below 89 LEs.    But I don't know that.  It could be that by using clever logic I could design a logic circuit that could do the same thing using only say, maybe 50 LEs.  It may be possible, or it may not be possible.  At this point in time I have no clue what the answer is.  And that's what I would like to know.

If it's impossible then so be it.  I will have my answer if that's the answer.

However, if it is possible to do the same thing using less gates by designing it directly in schematic format, then I'd want to take a look at how that could then be translated back into VHDL more efficiently.

In other words, what I will have actually discovered in the process is how to write more efficient VHDL code. 

If it turns out that my original VHDL code is already optimized for the ultimate efficiency, then I will have learned that as well.

So really I'm not trying to learn about FPGAs or Digital Logic but rather I'm trying to see how VHDL relates to describing digital logic.

In fact, this doesn't even necessarily require working in schematic mode.  I only chose schematic mode to work in because that's where I know I can implement the most "tricks" to save on gates.

Someone who is proficient in VHDL could probably just look at my VHDL code and say, "Hey I can improve on that code directly".

I mean, surely you can write sloppy VHDL code that will end up wasting gates or unnecessary LEs?

Like I say, the only reason I'm interested in doing this in schematic mode is because that's where I have the best chance to save on gates.

It's just a personal curiosity.    Once I have the answer to this question I can go have a beer. 

Until I know the answer I can't rest. 

[jackbob]

If you are trying to write your C program differently because your microcontroller only has 4K of flash, its time to upgrade your hardware. Likewise, if you are thinking so hard about saving a few LE's, you need a larger device. The VHDL synthesizer can be optimized to generate logic favoring either less LE's or faster speed. LE's are not everything, there are other considerations

But let's say you do figure out the minimum number of LE's to complete your task. What have you achieved? Maybe we have an area-efficient frequency divider now but was it worth the time and headache? Are we going to optimize all our designs using this method? Can your design spring a few extra bucks for some more LE's and practical development? In some cases for mass production, it is desirable to have an area-efficient design because we can use a cheaper device (maybe) but there are still other design and time constraints that make this level of optimization uncommon.

Also once we have the most area-efficient design, it more than likely will not be the fastest design. If your design has any moderately strict timing constraints, this requires a completely different design, one that sacrifices LE's for speed. 

[BrianHG]

You should be looking at not your coding, but features in the Quartus compiler to optimize the compile for Area instead of speed.  All of them, both in the compiler and in the fitter.

Also, in your VHDL, squeeze all your formulae into a single output register with no in-between steps.  Note that in some cases, it helps to actually spread out your design forcing and additional logic cell or 2 and disable the cascade logic features, or use WYSIWYG setting in the compiler.  You may get less gates in total, but, you will use an additional logic cell or 2.

[daybyter]

Did you try the various optimizer settings?

[james_s]

I've done loads of projects on that specific board, I love them, they're dirt cheap and compact, and despite being an older part they're powerful enough to fit an entire 8 bit computer system or retro arcade game within the FPGA. I released a number of bronze age Atari arcade games using it and some other odds & ends.

Forget about the schematic entry, it's a gimmick that is useful only for absolute beginners to get their feet wet. Once you get beyond a handful of gates it becomes extremely tedious, especially if you need to make changes or do debugging. Stick with VHDL (or Verilog) and it will save you enormous amounts of time and frustration in the long run. It's one of those things that I'm sure was used to demo in trade shows but in practice it's just awful and a complete waste of time. Schematic entry creates HDL under the hood, resource usage is influenced by the circuit design you use and the compiler settings, whether you describe that circuit visually with a schematic or in HDL. It's not as if the schematic is a whole separate thing, it's just a top layer that produces HDL that is handled internally by the same compiler that handles HDL you type in.

[jackbob]

I would also like to point out that if you optimized your circuit by had (i.e. minimum number of gates) this does not necessarily mean it will result in the minimum number of LE's. Even your schematic design is translated into VHDL then synthesized by the same compiler. Fewer gates does not always equal less LE's.

[Robo_Pi]

Ok, this whole thread is getting totally off-track from the original purpose.   My goal is to better understanding hardware description, NOT on trying to squeeze as much circuitry as I possibly can on a chip too small to hold it all.   So this is just getting totally off track.

I want to learn how to use the schematic features of Quartus II regardless of anyone's philosophical objections. 

So let's not go down that road.  I'll post my schematic questions on some other forum if they are going to cause such extreme adversity on this forum.

In the meantime since VHDL is the topic of interest here I have a question on VHDL:  So let's stick with that for now.

Here's the code: It's similar to the code in YouTube video I posted in the OP with very slight modifications.

This code takes in the 50 MHz onboard clock, reduces it to 1 Hz, and output a 6-bit binary counter.

Code: [Select]

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Binary_Counter is
port (
CLOCK : in std_logic;
reset : in std_logic;
LED : out std_logic_vector (5 downto 0)
);
end Binary_Counter;

architecture behavioral of Binary_Counter is
constant max_count : natural := 50000000;
signal op_Signal :std_logic;
signal theCount : std_logic_vector (5 downto 0);

begin
process(ClOCK)
variable count : natural range 0 to max_count;
begin
if(CLOCK'event and CLOCK='1' and count<(max_count/2)-1)
then op_Signal <= '1';
count:=count+1;
elsif(CLOCK'event and CLOCK='1' and count<max_count-1)
then op_Signal <= '0';
count:=count+1;
elsif(CLOCK'event and CLOCK='1' and count<max_count)
then op_Signal <= '1';
count:=0;
end if;
end process;

process(theCount)
begin
if(reset='0')
then theCount <= "000000";
elsif(op_Signal'event and op_Signal='1')
then theCount<=theCount+1;
end if;
end process;

LED<= not theCount;

end behavioral;

The code compiles with no errors, downloads onto the chip and runs perfectly as expected.

However, I do get the following two warnings that I would like to clean up.

Code: [Select]

Warning (10492): VHDL Process Statement warning at Binary_Counter.vhd(37): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list

Warning (10492): VHDL Process Statement warning at Binary_Counter.vhd(39): signal "op_Signal" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
I see in the code that "op_Signal" was defined as a signal after the architecture statement.  The "reset" signal was not mentioned.

But both of these signals show up as not being in the process statements "sensitivity list".

How to I correct this?

What do I need to do to place these signals in the "sensitivity list"?

[Robo_Pi]

I would also like to point out that if you optimized your circuit by had (i.e. minimum number of gates) this does not necessarily mean it will result in the minimum number of LE's. Even your schematic design is translated into VHDL then synthesized by the same compiler. Fewer gates does not always equal less LE's.

This is great.  Would you have any objections to me actually seeing these results for myself?  That's all I want to do.

I always encourage everyone to experiment and see for themselves how things actually work.

[Robo_Pi]

I've done loads of projects on that specific board, I love them, they're dirt cheap and compact, and despite being an older part they're powerful enough to fit an entire 8 bit computer system or retro arcade game within the FPGA. I released a number of bronze age Atari arcade games using it and some other odds & ends.

That's what I like about them too.  There cheap, durable, small, and uncluttered.   I don't need a board with a bunch of peripherals on it, so these are perfect for me.  I just want the barebones FPGA chip.  And that's what these boards have to offer.  So they are actually quite perfect for my experiments.

[jackbob]

I want to learn how to use the schematic features of Quartus II regardless of anyone's philosophical objections. 

Just say this from the beginning 

As for your problem here is the fix

Code: [Select]

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Binary_Counter is
port (
CLOCK : in std_logic;
reset : in std_logic;
LED : out std_logic_vector (5 downto 0)
);
end Binary_Counter;

architecture behavioral of Binary_Counter is
constant max_count : natural := 50000000;
signal op_Signal :std_logic;
signal theCount : std_logic_vector (5 downto 0);

begin
process(ClOCK)
variable count : natural range 0 to max_count;
begin
if(CLOCK'event and CLOCK='1' and count<(max_count/2)-1)
then op_Signal <= '1';
count:=count+1;
elsif(CLOCK'event and CLOCK='1' and count<max_count-1)
then op_Signal <= '0';
count:=count+1;
elsif(CLOCK'event and CLOCK='1' and count<max_count)
then op_Signal <= '1';
count:=0;
end if;
end process;

process(theCount, reset, op_Signal) ---------<---this is the sensitivity list----------------------
begin
if(reset='0')
then theCount <= "000000";
elsif(op_Signal'event and op_Signal='1')
then theCount<=theCount+1;
end if;
end process;

LED<= not theCount;

end behavioral;

The sensitivity list must contain any signals which change the output or behavior of your circuit when they change.

Basically, any signal in the sensitivity list makes the process statement (a sequential statement) be re-evaluated whenever any the state of any signal within the sensitivity list changes

[jackbob]

Also just as a word of advice, if the idea of an HDL is new to you, please try to learn the fundamentals first rather than just diving in and trying to follow some code. HDL is not like any other general purpose programming language at all. For example, you may know C and not have a clue about python, but from your C knowledge, you may be able to infer how a python program is behaving and learn just by studying prewritten code. The same is not true at all for HDL. HDL is fundamentally different how it operates.

I see in the code that "op_Signal" was defined as a signal after the architecture statement.  The "reset" signal was not mentioned.

The order which signals are defined in HDL does not matter, everything is concurrent outside of sequential processes. The reset signal lives in the entity as it is an external signal.

This is a great community with a lot of experts, people who could make me look dumb quite frankly. Don't leave to another forum because you don't like our feedback, if the people on another forum are knowledgeable about the subject, they will say the same as us. We are here to help and are just trying to encourage best practices from experience 

[james_s]

One of the most important things to understand about HDL is that it's not a programming language. It's a *hardware* description language, which superficially resembles a programming language but it isn't a program. The instructions are not executed, they're used to describe a schematic just as one could translate a schematic into English to describe a circuit to someone over the phone. I actually think that previous programming experience can be more hindrance than help when it comes to learning VHDL or Verilog.

[Robo_Pi]

One of the most important things to understand about HDL is that it's not a programming language. It's a *hardware* description language, which superficially resembles a programming language but it isn't a program. The instructions are not executed, they're used to describe a schematic just as one could translate a schematic into English to describe a circuit to someone over the phone. I actually think that previous programming experience can be more hindrance than help when it comes to learning VHDL or Verilog.

I'm well aware that VHDL is a "Hardware Description Language" that is quite different from a programming language.   In fact, this was my whole purpose of getting some insight into how VHDL describes actual schematic circuits.  This is why in the early going I would like to go back and forth between extremely simple schematics and VHDL.   That was really my whole purpose.  I wanted to see how VHDL relates to a hardware schematic that I already understand.  The idea of "saving gates" was merely an aside.  In fact, what I was thinking about there was not actually saving gates at all, but rather that this is something that I could potentially do to see how VHDL relates to the hardware.

If I could "save gates" then I could surely go back and rewrite the VHDL to reproduce the new "hardware" circuit that I had just designed by hand.  It's not so much that I would have saved gates, but rather I would have learned what it takes to write more efficient VHDL.

This is precisely why I want to learn how to do the schematic design in Quartus II.  Not with the intent of ever actually creating a full blown design from the schematic level. 

I'll definitely end up working almost exclusively in VHDL eventually, I have no doubt about that.   Or possibly Verilog.  I would also like to learn how to describe hardware using a Finite State Machine too.   I want to learn all of this stuff eventually.   But I need to start with the basics.

[Robo_Pi]

I would recommend the Free Range VHDL book

By the way jackbob, I downloaded the book you recommended.   I'll definitely be reading that baby though cover-to-cover.

But I just wanted to point out a few things the book says in the section 1.1 Golden Rules of VHDL

Before you start, here are a couple of points that you should never forget when working with VHDL.
VHDL is a hardware-design language. Although most people have probably already been exposed to some type of higher-level computer language, these skills are only indirectly applicable to VHDL. When you are working with VHDL, you are not programming, you are “designing hardware”. Your VHDL code should re?ect this fact. What does this mean? It means that unless you are inside certain constructs, your code lines will be executed almost all at once. If your VHDL code appears too similar to code of a higher-level computer language, it is probably bad VHDL code. This is vitally important.

This is exactly what I'm talking about trying to avoid.  Clearly VHDL can be written 'badly'.

Have a general concept of what your hardware should look like. Although VHDL is vastly powerful, if you do not understand basic digital constructs, you will probably be unable to generate e?cient digital circuits. Digital design is similar to higher-level language programming in that even the most complicated programming at any level can be broken down into some simple programming constructs. There is a strong analogy to digital design in that even the most complicated digital circuits can be described in terms of basic digital constructs. In other words, if you are not able to roughly envision the digital circuit you are trying to model in terms of basic digital circuits, you will probably misuse VHDL, thus angering the VHDL gods. VHDL is cool, but it is not as magical as it initially appears to be.

This is exactly what I'm trying to do.  I'm trying to avoid angering the VHDL gods. 

I want to gain a very solid connection between what I'm trying to produce in hardware before I start going crazy writing 'bad' VHDL code.

This is why I would like to get at least some feel for how various simple circuits look in both VHDL and Schematic form.

I personally thought this would appease the VHDL gods quite a bit.   But thus far on this forum I've almost been burned at the stake for suggesting that I would like to gain insight into how circuits relate to VHDL and vice versa.

Everyone is suggesting that I should stay way from the schematics.  But the book you've recommended doesn't seem to be suggesting this at all.

[NivagSwerdna]

FWIW I didn't know any HDL a month a go... this is what I did (after recommendations in another thread)...

I read Digital Design and Computer Architecture: ARM Edition by [Harris, Sarah, Harris, David]  (managed to find a cheap 2nd hand copy)
& I played along to https://people.ece.cornell.edu/land/courses/ece5760/index_old.html which is the Spartan II variant of the Cornell FPGA class (lots of youtube videos)
& I've read a lot of source from https://github.com/MiSTer-devel/Main_MiSTer/wiki as examples

But... Quartus II does seem a bit of a mystery.  I discovered the megwizard by accident but this is very useful for getting started... e.g. dividing down the clock with a shift register.

[jackbob]

Very good read this book and you will please the gods! 

That book is an excellent resource for any beginner, it was my introduction to VHDL. Once you understand the core principles of the HDL you can advance to other more advanced resources focusing more on design strategies using VHDL rather than the basics of VHDL. Once you read the book and understand it, write a few VHDL "programs" and you will see exactly what we mean about the schematic editor (I was in the same boat as you).

The book doesn't explicitly say to stay away from the schematic editor but it does say this on page 7

Modeling digital circuits with VHDL is a form of modern digital design distinct from schematic-based approaches. The programmer writes a loose description of what the final logic circuit should do and a language compiler, in this case called a synthesizer, attempts to “infer” what the actual final physical logic circuit should be.

This is pretty much what I was trying to get at.

Anyways... Please feel welcomed here. I joined this forum as a freshman in high school and have felt the same way. I started out not knowing anything and was intimidated to ask questions. Many years later I realize how valuable of a resource forums can be and here I am trying to help others and give back 

I would also recommend watching my video series as well. Like I said it's based on the free range book and I am spending countless hours putting this series together to help people in a similar position. I wish I had a comprehensive series of videos to learn FPGA's and VHDL when I first started.

Welcome to the community and happy learning 

[james_s]

It's certainly possible to write bad VHDL, likewise you can create a bad schematic that may work to some degree but be far from optimal. A point I've tried to make about the schematic is that all it's doing is spitting out VHDL descriptors of each gate or IC you draw when is then piped into the same synthesizer as you would use by describing the circuit yourself in VHDL. Whether you draw the circuit or describe it in code the result is going to depend on how sensibly you do so.

[NivagSwerdna]

Old Video but Bill seems a jolly type.