Artix-7 GTP transceiver as delta-sigma DAC

[OwO]

In my past experiments with synchronous delta-sigma modulators, I found that it was sufficient to have a bit clock 10 to 20 times the highest signal frequency to get audio-level signal quality (probably 70-80dB SNR). In theory with a 3Gb/s transmitter I could output up to 200-300MHz signals at ~14 bits fidelity, which is useful for SDR applications. The GTP differential output would go into a balun and then a lowpass filter. In theory as long as the filter components don't distort the signal the output linearity should be very good.

Has anyone thought of doing something similar? For devices without GTP the LVDS transmitter can be used too. I'm going to implement a lookahead delta-sigma modulator where several output bits are predicted at a time so that 3Gb/s streams can be generated from slow logic.

[mark03]

I haven't tried it yet, but I was recently playing with this design/simulation tool:  http://www.python-deltasigma.io/
and wondered if a bandpass DSM might be the ultimate in reduced-parts-count RF signal generation for SDR.  I thought of doing pretty much what you are describing, with an LVDS output pair on a Spartan 7 feeding a differential band-pass filter for, say, 14 MHz.  If you try this I'd be very curious to know the performance, esp. the phase-noise performance.

On the con side, RF DACs are small, cheap, and low power, so it's kind of hard to justify not using one.  But this would be more *fun*.

Edit:  Note that in a bandpass DSM the noise shaping is designed to favor a bandpass (not the band around DC), so less extreme sampling rates can still be used (and better than 14 bits can be achieved).  At least in theory.  There may be practical limitations I have not considered.

[NiHaoMike]

It's also possible to implement an ADC with a FPGA, something that I'm considering using for an inverter project I'm working on.
https://hackaday.com/2015/09/09/video-fpga-with-no-external-ad/

[ejeffrey]

I have thought about this and would be really interested to hear about any results.  I would be worried that the current mode logic outputs will not be as suitable for sigma delta converters as hard switched CMOS logic.  Also serdes outputs don't usually have a precision reference so the amplitude accuracy and stability likely won't be as good as a regular DAC.  Still, it might still be quite good for some applications at least.

[mark03]

Well I guess someone needs to try it

FWIW, the python deltasigma toolkit gives me this for a 6th-order bandpass DSM (single-bit output) running at 320 MHz, with a passband centered at 14.0 MHz:



The usable passband is from about 13.4 to 14.6 MHz.  The coefs to use in a CRFB structure are

Code: [Select]

a=[-0.00277981 -0.00687177 -0.05191883  0.06511814  0.15092094  0.55559864]
g=[0.26110259 0.27057312 0.28019991]
b=[-0.00277981  0.          0.          0.          0.          0.
  0.        ]
c=[1. 1. 1. 1. 1. 1.]

Edit:  Here's a block diagram of a 6th-order CRFB structure, cribbed from a paper.  The c's can be ignored and b0 is just a multiplier on u(n).



I've never actually tried my own delta-sigma stuff, so I don't know what the achievable speed would be.  The structure does have a critical path where several things need to be multiplied by different coefs and then summed before being registered.

[SiliconWizard]

FWIW, the python deltasigma toolkit gives me this for a 6th-order bandpass DSM (single-bit output) running at 320 MHz, with a passband centered at 14.0 MHz:

This is cool and interesting as an illustration, but are you sure you can really run a 6-th order DSM @320MHz on an mid-end FPGA?

[mark03]

FWIW, the python deltasigma toolkit gives me this for a 6th-order bandpass DSM (single-bit output) running at 320 MHz, with a passband centered at 14.0 MHz:

This is cool and interesting as an illustration, but are you sure you can really run a 6-th order DSM @320MHz on an mid-end FPGA?

No.  But I know very little in this area.  Maybe there are alternative structures?

[OwO]

300MHz isn't hard to do for this kind of layout with only an adder between registers, but that isn't good enough for gigabit speeds and what I'll need to do is predict the system state some tens of clock cycles later. Every FPGA clock cycle it must compute the next N output values and the state variables at time +N. This is easy to do for a first order lowpass DSM where there is a single state variable and it's equal to the integral of the input (mod 2^b). I'll need to see what can be done for higher order DSM.

Meanwhile I'm designing an Artix board:
(GTX are at the top and bottom sides of the device)

[SiliconWizard]

Took a look at a past project in which I implemented a 2nd order SDM, with 32-bit data width, 48-bit accumulator width, 512x oversampling factor, and a simple linear interpolation as filtering.

(As I remember, increasing bit width would allow to meet the requirements in terms of distortion without having to implement more sophisticated filtering, which was actually more expensive in terms of area and max speed even with significantly lower bit width... You can actually see that confirmed when looking at the "relatively" low-cost 32-bit audio DACs out there, with specs barely matching those of a mid-range 24-bit DAC. Turns out less expensive and simpler to implement. Of course to take advantage of it, you need to feed it with true 32-bit samples, which was not a problem in my case as it was actually the native format.)

I was clocking it at 100MHz. The report shows an estimated max frequency of 690MHz (on a Spartan 6), not sure how much I can trust this, as it looks very optimistic. But yes, 300MHz should definitely be easy to reach if you implement it carefully and use simple filters.