Atmel ATF150x CPLD and WinCUPL

[TomS_]

Do you have to maintain 12V on the OE pin to keep the JTAG port open, or only on power up?

If only on power up, I wonder if you could remove 12V from OE1 once youve established that JTAG is working, send in the erase command, and then do a 100ms pulse of 12V perhaps? If that is what is meant by an "erase pulse" anyway.

Otherwise yeah, send a support request to Microchip and see if they will give you anything. Very interesting stuff though!

Otherwise I wonder if there is any documentation for the MAX7000 series around that shows the programming/erase waveforms and whether they would happen to be the same. I did try searching the other day but it was late so I didnt get too far.

[maginnovision]

I know the conversation has shifted somewhat but if you ever do use wincupl I recommend removing any of the optimizations as they sometimes fail to create equations that match the originals. It's best to compare the output to what you wrote if you do run into any issues. Generally it actually does exactly what it says, it just doesn't do what you asked when you attempted to compile. Also when you flash you need to re-select the file since atmisp caches the .jed.

[LittleRain]

Unfortunately there isn't a free toolchain for VHDL or Verilog (I havent used them either(!) but there are more examples on the net).

Page 3, says Prochip Designer is free.

Can download from here, although you need to be approved before you can actually download.
I just put in an application, so I'm not sure how the process really works.


I know this is an old post, but I thought the original poster would be happy to know about it, as well as anyone else interested in Atmel CPLDs.

[oPossum]

They will give you a free 30 day eval. After that is is $600 for a 2 year license. Part # ATDS15xxKSW1

[shutay]

I'm rather late to the party, but you might want to consider this open source tool by H. Neeman, called "Digital", which unfortunately makes it very hard to find using Google if you only know the name of the tool. It is a schematic entry simulation software written in Java that, working together with the fitter tools from WinCUPL (which needs to be installed alongside it), can generate the necessary files to program the ATF150x series CPLDs (via ATMISP 7.0, which also needs to be installed). It seems to be actively supported, and version 0.27 was released just 10 days ago. Remember to tell Digital where to find WinCUPL and ATMISP in the settings dialog.

https://github.com/hneemann/Digital

Supported devices: GAL16v8, GAL22v10, ATF1502 (TQFP & PLCC), ATF1504 (TQFP & PLCC44), ATF1508 (PLCC84 only).
You can also check out this series of videos produced by Douglas Gabbard on YouTube: https://youtu.be/4LYgWtVbT2s

I have been using them with the ATF1504AS PLCC44 chips and can confirm that at least for my needs, it has served me well (WinCUPL keeps crashing on me).
It can take a truth table and generate logic based on NAND gates or NOR gates, or LUTS, export Verilog or VHDL. It does not allow a circuit to be defined in HDL, AFAIK. To me, this tool alone can help make the ATF150x series more popular again. If not, then more usable.

Best, Jason