Hi,
If I read and write to a simple reg on the same rising clock edge, is the read value guaranteed to be the old data?
I.e:
reg[15:0] myreg = 0;
...
always @ (posedge clk)
begin
output_reg <= myreg;
myreg <= myreg + 1;
end
output_reg is guaranteed to be the non-incremented (old) value, right?