Electronics > FPGA

Being Stuck with Efinix

<< < (4/5) > >>

glenenglish:
0.8mm is easy for standard JLCPCB .

make the vias under the FPGA  0.2mm / 0.48mm and use 0.1mm trace and space to route under FPGA
use 1mm or 1.2mm for 6 layer PCB to keep capacitances between layers high (embedded capacitance) . Preferably  0.1mm between VCCcore and GND.
and extend beyond FPGA region a bit to maximize decoupling.

dont pour tight on inner layers (extra pullback)  --- IE dont make it hard for yourself or the vendor un-necessarily.
relax everyone otherwise FPGA region. can be done in 6 layers if you are smart with VCCIO regions.

adamarrrrr:
I echo 0.8mm BGA being easily achievable with the standard JLCPCB process (and as a bonus if your board is under 5x5cm, you can get a 6 layer board for under $5 with ENIG and via-in-pad for prototypes). You can also get away with a 4 layer board by routing power smartly on the bottom/3rd layer, or just dedicating the entire 3rd layer to power. Obviously you lose out on any inter-plane capacitance and bottom layer routing/SI becomes a lot trickier because not everything is referenced to ground anymore.

I've only worked with their Ti60 series, but I got my prototype PCB pretty much working 100% first try based on their app notes and reference board, and I NEVER get things right. So +1 to them! The only thing I wasn't able to confirm working was programming the flash through SPI directly. I tried using their 'active' SPI programming method where the FPGA provides the clock signal, and the FT2232 is treated like a slave device (so you don't have to do any disconnecting), but no such luck. I expect this is my fault, as my module uses 0.5mm BTB connectors that seem very averse to hand soldering and alignment and working in general.

Their weird and very-not-streamlined JTAG-bridge solution seemed to work though. It basically involves their software pushing two separate files to the FPGA via JTAG - one is the JTAG bridge that you have to manually generate for your specific design for some reason(?), and the other being your actual file you want to flash to your memory device. I've worked with Lattice/Xilinx parts where the bridge method is literally only one click, so it seems a bit odd. Their software is also VERY SLOW, yet very basic. The synthesis speed is fine, just that opening any menu takes literally 10-30 seconds for some reason, especially the interface designer.

For reference: 0.65mm BGA on a 4 layer board (with 0.35mm vias) from JLCPCB. Unfortunately the smaller vias cost extra $$$ from their standard process.

gnuarm:
I had decided to go with the T13F256/T20F256 (not a big difference in price).  Then, recently I've read they are now coming out with 100QFP parts!  But... the engineering samples aren't even available until Oct.  Too late for my project.

AndyC_772:
100QFP? I like that idea, much easier to deal with than the FBGA169 which is the package I've ended up using.

Let's just hope they don't waste half the pins on a MIPI interface this time.

[Edit]: the updated data sheet is on the web site, no MIPI, and there's an internal SPI Flash too.

gnuarm:
I didn't notice the Flash.  That's pretty sweet!  I just can't wait until October to even get engineering samples. 

Navigation

[0] Message Index

[#] Next page

[*] Previous page