Electronics > FPGA

Bram Memory Size Configuration


Dev Board: tang nano 9k
DataSheet: http://cdn.gowinsemi.com.cn/DS117E.pdf
page 35-36 table 2-4

The datasheet page 35 says each block of bram is 18,432bits. Page 36, Table 2-4 shows a configurable block size of "2K x 8". Is this table an approximation of the the bits available, or a hard value? Do I lose 2,432bits just by using this a "2k x 8" configuration?
I have noticed this trend in many datasheets.

It is normal for block ram to have a 'parity bit', allowing a 9-bit, 18-bit or 36-bit interface.

See section 2.2 of https://cdn.gowinsemi.com.cn/UG285E.pdf for allowed modes.

Thank you for the info, seams like an easy question, after reading the ds again and the user guide you posted, there is not a simple yes or no answer as I was expecting. It looks as tho, in the mode I want only 2048 bytes (16384 bits) will be available.
Even more details than the datasheet, page 13, heres another "got ya" I missed

--- Quote ---GW1N-9/GW1N-1S/GW1NR-9/GW1NS-4 series does not support dual port mode
--- End quote ---

This leads me to ask about usage, specifically addressing, on page 11(same page you referenced). When I assert an address onto the .... wait, page 26, example code....
Thank you again hamster_nz.


--- Quote from: hamster_nz on February 09, 2024, 12:55:00 am ---It is normal for block ram to have a 'parity bit', allowing a 9-bit, 18-bit or 36-bit interface.

--- End quote ---
Is there a standard to the parity bit position?
That question just feels vague.
It looks as tho there will be a parity bit for every 8 bits(byte). 8+1=9    2(8+1)=18    4(8+1)=36
What in trying to ask is, all the parity bits all grouped together at the end of the register, or distributed after each byte?
Or just personal preference?

Parity Bits*

* serving suggestion

Its just a 9/18/36/72 bit wide ram with 2^n addressing, you can use the bits however you want.


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