Author Topic: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.  (Read 23264 times)

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Online BrianHG

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Re: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.50.
« Reply #150 on: April 11, 2022, 03:25:40 am »
Note that the purpose of my multiport was to make my DDR3 controller's interface to appear exactly like a 16 port altsyncram FPGA blockram function.  You just need to be attentive to the CMD_busy when read or writing and wait for the CMD_read_ready to see your read request ohhh so may clock cycles later.  So, to get the full read performance, you need to remember to post a bunch of reads ahead of time.  My CMD_read vector in/out ports does some lifting offering you a means of delineating a destination for each posted read command.
« Last Edit: April 11, 2022, 03:30:52 am by BrianHG »
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Re: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.50.
« Reply #151 on: May 23, 2022, 07:36:50 pm »
Version 1.6 update...

 :palm: After 3 days of work and test compiles, I finally found my Quarter Rate setting bug.  And I flew by it a dozen times...

   I forgot to clock latch in the read_data_valid_toggle signal going from the half-rate clock domain to the quarter rate domain.  With heavy reads, that toggle signal may come in on the first or second half of the Quarter clock's period.  When operating in Half-rate, there is no Quarter rate and that latch always arrives by the next clock, so no problem.  At Quarter rate, usually, with slow memory single reads, or continuous evenly length bursts, that latch signal just happens to always be aligned at the beginning of the Quarter rate clock maintaining proper function.  But with bursts with just the right pacing and an odd length buried inside, like when my multi-window VGA generator has 2 super-imposed windows, one with an odd number of pixels just at the right position, then a read data valid may align itself to the second half of the Quarter-rate clock as the DDR3 controller may have an odd number of half-rate clock cycles until the read_data_valid_toggle.  This causes a loss of synchronization as that read is latched at the wrong time with the wrong vector data used by my multiport commander to know when a read arrives and which port the read data belongs to.

   After 3 days, I thought I had a fundamental architecture problem, but no...  :phew:  However, along the way, I added a few new features and further improved the .sdc constraints rendering a further improvement in achieving a high level FMAX.

Full proper release DDR3 v1.6 with VGA controller will come in a day after I clean up my mess.
« Last Edit: May 23, 2022, 07:41:54 pm by BrianHG »
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Re: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.50.
« Reply #152 on: May 24, 2022, 12:15:12 am »
Arrrrgggg, ok, for my changes, once I removed my watch dog timer, it works fine for 30 seconds or so, but still seizes up.  Still superior to instantly seizing up, or garbage reads, but there must be another signal somewhere interrupting the system.  It also wont seize up if I use just the video channel, but start the RS232 debugger and it eventually craps out.  Yet in half-rate, everything runs AOK.
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Re: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.50.
« Reply #153 on: June 11, 2022, 02:33:29 am »
Release V1.6 Demo .sof programming files of DECA BrianHG_DDR3_Controller v1.6 and multi-window BrianHG_GFX_VGA_Window_System v1.6 for Arrow DECA eval board.

  >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D
  >:D  500MHz/1GTPS! with 2x32bit 1080p60 video layers.    >:D
  >:D  That's >1100 megabytes/sec just to show the image,  >:D
  >:D  never mind simultaneously drawing all those ellipses.  >:D
  >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D >:D

Just open your JTAG programmer and add one of the following 2 files:
1. 'BrianHG_DDR3_DECA_GFX_DEMO_v16_1_LAYER_500MHzQR.sof'
        -> Replaces and replicates the original Ellipse Generator now using the new BrianHG_GFX_VGA_Window_System.

2. 'BrianHG_DDR3_DECA_GFX_DEMO_v16_2_LAYERS_500MHzQR.sof'
        -> Improved original Ellipse Generator demo where a second translucent superimposed video window scrolls at different coordinates and speeds generating an LSD trip visual effect.  (Note that the scroll switch needs to be turned on long enough at least bounce off 1 window edge to view effect.)

Check-on the 'Program/Configure' and click 'Start' to program.
The DECA's HDMI should output a 1080p image.


IMPORTANT NOTE:
If the picture is still or scrolling noise, just press buttons 0 or 1, or flip 'Switch 0' to enable drawing ellipses.  You just powered up the demo in frozen picture mode and you are looking at the powered up random blank memory.


Switch 0 = Enable/Disable drawing of ellipses.
Switch 1 = Enable/Disable screen scrolling.
Button 0 = Draw data from random noise generator.
Button 1 = Draw color image data from a binary counter.

Full Github v1.6 source code.
https://github.com/BrianHGinc/BrianHG-DDR3-Controller
« Last Edit: June 13, 2022, 08:46:23 pm by BrianHG »
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Re: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.50.
« Reply #154 on: June 12, 2022, 03:23:46 am »
New VGA video system demo configured for up to 16 window layers driven by my RS232_Debugger.  :box:

Code: [Select]
//****************************************************************************************************************
//
// Demo documentation.
//
// BrianHG_DDR3_DECA_GFX_HWREGS_v16_16_LAYERS which test runs the BrianHG_DDR3_CONTROLLER_top_v16
// DDR3 controller with the BrianHG_GFX_VGA_Window_System_DDR3_REGS.
//
// Version 1.60, June 9, 2022.
//
// Written by Brian Guralnick.
// For public use.
// Leave questions in the [url]https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/[/url]
//
//****************************************************************************************************************

A pre-built DECA compatible programming .sof file : BrianHG_DDR3_DECA_GFX_HWREGS_v16_16_LAYERS.sof should be used for this demo.

This demo requires a PC with a RS232 <-> 3.3v LVTTL converter and the use of my RS232 debugger to live edit window controls.
All necessary files are found in this project's sub-folder 'RS232_debugger'.

Wiring: On DECA PCB, connector P8.
    P8-Pin 2 - GND            <-> PC GND
    P8-Pin 4 - GPIO0_D[1] out --> PC LVTTL RXD
    P8-Pin 6 - GPIO0_D[3] in  <-- PC LVTTL TXD

See Readme.txt file in the .zip for full documentation.
See 'BrianHG_GFX_VGA_Window_System.txt' for address controls.
See 'BrianHG_GFX_VGA_Window_System.pdf' for system block diagram.
« Last Edit: June 12, 2022, 03:26:54 am by BrianHG »
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Re: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.
« Reply #155 on: June 12, 2022, 07:32:56 pm »
As of today, full Github v1.6 source code has now been released:

https://github.com/BrianHGinc/BrianHG-DDR3-Controller

Expect 300Mhz-350Mhz builds to always meet timing requirements.  (Even with a slow fabric -8.)
Expect 400Mhz builds to usually meet timing requirements with the occasional need to massage some compiler/fitter settings to aid in meeting timing requirements.  (Still easier than making Altera's paid Uniphy DDR3 controller achieve only 300Mhz.)
Expect Cyclone III/IV -6 can meet timing requirements at 450MHz.  Even 500MHz is possible with heavy massaging of fitter setting.

Expect my BrianHG_GFX_VGA_Window_System to run up to 32 windows in 480p, 16 in 720p, 8 in 1080p.
Also expect my BrianHG_GFX_VGA_Window_System to automatically simplify down to minimal gates when lowering layers down to 1, disabling palette / font/tile modes and hard-wiring numerous video/window setting.
« Last Edit: June 13, 2022, 02:18:18 am by BrianHG »
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Re: BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.
« Reply #156 on: July 12, 2022, 09:27:20 pm »


 :-DD I bet 'evb149' just needed the 'LSD trip visual effect'...
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