Electronics > FPGA
BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.
BrianHG:
As of today, full Github v1.6 source code has now been released:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller
Expect 300Mhz-350Mhz builds to always meet timing requirements. (Even with a slow fabric -8.)
Expect 400Mhz builds to usually meet timing requirements with the occasional need to massage some compiler/fitter settings to aid in meeting timing requirements. (Still easier than making Altera's paid Uniphy DDR3 controller achieve only 300Mhz.)
Expect Cyclone III/IV -6 can meet timing requirements at 450MHz. Even 500MHz is possible with heavy massaging of fitter setting.
Expect my BrianHG_GFX_VGA_Window_System to run up to 32 windows in 480p, 16 in 720p, 8 in 1080p.
Also expect my BrianHG_GFX_VGA_Window_System to automatically simplify down to minimal gates when lowering layers down to 1, disabling palette / font/tile modes and hard-wiring numerous video/window setting.
SpacedCowboy:
I just ordered one of these (apparently new) Gowin 20k boards. I'm going to see if I can port your design across, which is going to be ... challenging ... because I know little about DDR3 and nothing at all about Gowin, but if I can get it working, having a pre-built DDR3/FPGA board with that many GPIO for that price in an easily-embeddable DIMM is going to be kinda useful :)
BrianHG:
--- Quote from: SpacedCowboy on August 22, 2022, 06:36:18 pm ---I just ordered one of these (apparently new) Gowin 20k boards. I'm going to see if I can port your design across, which is going to be ... challenging ... because I know little about DDR3 and nothing at all about Gowin, but if I can get it working, having a pre-built DDR3/FPGA board with that many GPIO for that price in an easily-embeddable DIMM is going to be kinda useful :)
--- End quote ---
Begin with nothing more than implementing my simple 'BrianHG_DDR3_PHY_SEQ' controller. It is half the size and once you got that working, implementing the multiport with everything else will be much easier as they have no special code and are only needed if you need 16 read/write ports.
So long as Gowin can deal with System Verilog, the only 2 HDL modules you will have to adapt will be:
BrianHG_DDR3_PLL.sv
BrianHG_DDR3_IO_PORT_ALTERA.sv
If Gowin uses or can use Modelsim, this will be a great help as I have already set all this up. I still do recommend downloading Altera/Intel's free Quartus's v20.1 (not v21.x) and at least install that Modelsim as it has Altera's PLL and DDR_IO libraries so you can see what the original supposed to look like as I created setup_xxx.do script files which simulate everything individually. Don't worry, you may have multiple versions of Modelsim in you system at the same time.
This link: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_DECA_PHY_SEQ_only_v16
Contains my simple stand alone 'BrianHG_DDR3_PHY_SEQ' controller wired to my RS232 debugger allowing you to view and edit the DDR3 memory contents from a PC with a LVTTL <-> RS232 com port, and it will report DDR3 tuning status and you can leave it running while updating you Gowin firmware. Documentation is on my Github's read-me.
Step #1 would be to see if you can simulate a Gowin PLL with the phase step up and phase step down controls my DDR3 controller requires. This means concentrating exclusively on replicating nothing more than my 'BrianHG_DDR3_PLL.sv' and it's stand alone testbench with it's 4 clock outputs. If you are lucky, Gowin should provide their own PLL library functions in their own simulator.
SpacedCowboy:
Thanks Brian,
--- Quote ---Step #1 would be to see if you can simulate a Gowin PLL with the phase step up and phase step down controls my DDR3 controller requires. This means concentrating exclusively on replicating nothing more than my 'BrianHG_DDR3_PLL.sv' and it's stand alone testbench with it's 4 clock outputs. If you are lucky, Gowin should provide their own PLL library functions in their own simulator.
--- End quote ---
So this just got harder..
'Gowin' and 'Simulator' seem to be words that do not exist in the same sentence, other than in sentences where "do not have one" also appear... And this is in the "licensed" (ie: please send us your email) version, not the 'educational'
one.
There used to be an option in the IDE (I've seen screenshots!) where you could call into a 3rd party simulator, but that seems to have been removed (why ?!) There is an option to generate .vo "post-PnR simulation model files" in the options, but other than that there's sweet Fanny Adams to help out.
Clearly it'd be useful to have the same simulation environment as you're using, but I don't have Modelsim, and I can't find out how expensive it is... I sent off an email to the 'contact us' page at Siemens, but I have a bad feeling about software that doesn't advertise its price *anywhere*... Even my most recent eye-wateringly-expensive purchase (Altium) had advertised prices...
On the upside, it looks as though System Verilog (2017) is supported. And the boards I bought have shipped straight away, which is nice. It's been many (many!) moons since I could claim a student version of anything (and anyway it looks as though they've removed the free student edition for now), so on the down-side, I may be using icarus verilog or something similar...
BrianHG:
--- Quote from: SpacedCowboy on August 23, 2022, 01:44:36 am ---Clearly it'd be useful to have the same simulation environment as you're using, but I don't have Modelsim, and I can't find out how expensive it is... I sent off an email to the 'contact us' page at Siemens, but I have a bad feeling about software that doesn't advertise its price *anywhere*... Even my most recent eye-wateringly-expensive purchase (Altium) had advertised prices...
--- End quote ---
Modelsim is free. It comes with Quartus 20.1 free web version and earlier. (Includes Quartus Megafunction Libraries.)
It also comes with Lattice Diamond Design Software 3.12 and later. (This version includes Lattice's library functions.)
I do not know about Gowin.
If you do not include the appropriate -L xxxxx on the compile line to include the vendor's library functions, then it's a basic Modelsim with over 90% functionality. There are only 1 or 2 advanced post generation function views which arent available unless you buy the full Modelsim, but these are available in Quartus and Lattice itself.
I personally begun to completely develop in Modelsim alone and then move my design to the FPGA tools as Modelsim's compile/build time is usually within a second.
Try googling:
HDL modelsim gowin fpga
and
HDL Active-HDL gowin fpga
Active-HDL is a somewhat close to but a cheaper experience than Modelsim.
Take a look at my https://github.com/BrianHGinc/SystemVerilog-TestBench-BPM-picture-generator as I made it work for both simulators. Only difference is in the setup-xxx.do files.
You can look here:
https://www.intel.com/content/www/us/en/software-kit/661015/intel-quartus-prime-standard-edition-design-software-version-20-1-for-windows.html and click on 'Individual Files' where you will see Modelsim as a stand-alone download.
But the listed modelsim there only has the added Altera/Intel libraries, yet almost everything else works.
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