Electronics > FPGA

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

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BrianHG:
As of today, full Github v1.6 source code has now been released:

https://github.com/BrianHGinc/BrianHG-DDR3-Controller

Expect 300Mhz-350Mhz builds to always meet timing requirements.  (Even with a slow fabric -8.)
Expect 400Mhz builds to usually meet timing requirements with the occasional need to massage some compiler/fitter settings to aid in meeting timing requirements.  (Still easier than making Altera's paid Uniphy DDR3 controller achieve only 300Mhz.)
Expect Cyclone III/IV -6 can meet timing requirements at 450MHz.  Even 500MHz is possible with heavy massaging of fitter setting.

Expect my BrianHG_GFX_VGA_Window_System to run up to 32 windows in 480p, 16 in 720p, 8 in 1080p.
Also expect my BrianHG_GFX_VGA_Window_System to automatically simplify down to minimal gates when lowering layers down to 1, disabling palette / font/tile modes and hard-wiring numerous video/window setting.

BrianHG:


 :-DD I bet 'evb149' just needed the 'LSD trip visual effect'...

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