Electronics > FPGA
BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.
asmi:
--- Quote from: BrianHG on December 22, 2022, 03:41:54 am ---@asmi, I'm sorry, but I cannot guarantee I will have enough free time over the next 3 months to do work on adapting my DDR3 controller to Lattice. It's a shame that we didn't do this back in September.
--- End quote ---
No worries, that's OK, I understand, we all have a life to live.
gvedaraj:
Hi Brian,
Just a quick question regarding the DDR3 controller. The README page says that it is designed for Cyclone 3/4/5 boards. But I see that Cyclone 3/4 supports only till DDR2.
Does that mean that the controller works for both DDR2/DDR and DDR3 memories?
Thanks & Regards
Ganesha
BrianHG:
--- Quote from: gvedaraj on January 21, 2023, 11:29:37 pm ---Hi Brian,
Just a quick question regarding the DDR3 controller. The README page says that it is designed for Cyclone 3/4/5 boards. But I see that Cyclone 3/4 supports only till DDR2.
Does that mean that the controller works for both DDR2/DDR and DDR3 memories?
Thanks & Regards
Ganesha
--- End quote ---
No, it means wire DDR3s to a Cyclone III or Cyclone IV and it will work.
I use a trick with Altera's PLL to generate alternate read phase clock and write phase clock which are self tuned during power-up to operate the ram. I measure and use the DQS as a clock enable instead of as a clocking port for the DQ read data. This permits me to control 1 or 2 16bit DDR3s on the older cyclones. Or 4x 8bit ones.
Use the 1.5v HSTL CLASS I IOs and DDR3 IO voltage. See photos and instructions of my pinouts pin-planner on my Github and review my hypothetical Cyclone III/IV examples which compile and meet timing requirements to see how to setup.
Example Cyclone III setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIII_GFX_TEST_v16_1_LAYER_Q13.0sp1
Example Cyclone IV setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIV_GFX_TEST_v16_1_LAYER
Pin planner read-me: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/Screenshots_Pin_Planner
gvedaraj:
--- Quote from: BrianHG on January 22, 2023, 09:28:56 am ---
--- Quote from: gvedaraj on January 21, 2023, 11:29:37 pm ---Hi Brian,
Just a quick question regarding the DDR3 controller. The README page says that it is designed for Cyclone 3/4/5 boards. But I see that Cyclone 3/4 supports only till DDR2.
Does that mean that the controller works for both DDR2/DDR and DDR3 memories?
Thanks & Regards
Ganesha
--- End quote ---
No, it means wire DDR3s to a Cyclone III or Cyclone IV and it will work.
I use a trick with Altera's PLL to generate alternate read phase clock and write phase clock which are self tuned during power-up to operate the ram. I measure and use the DQS as a clock enable instead of as a clocking port for the DQ read data. This permits me to control 1 or 2 16bit DDR3s on the older cyclones. Or 4x 8bit ones.
Use the 1.5v HSTL CLASS I IOs and DDR3 IO voltage. See photos and instructions of my pinouts pin-planner on my Github and review my hypothetical Cyclone III/IV examples which compile and meet timing requirements to see how to setup.
Example Cyclone III setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIII_GFX_TEST_v16_1_LAYER_Q13.0sp1
Example Cyclone IV setup using 1x 16bit DDR3: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/BrianHG_DDR3_CIV_GFX_TEST_v16_1_LAYER
Pin planner read-me: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/tree/main/Screenshots_Pin_Planner
--- End quote ---
Thanks a lot for the sharing these resources!!
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