Electronics > FPGA
BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.
BrianHG:
New PLL v1.4.
PLL now supports up to 1GHz for Arria V and Cyclone V, this means up to 2gtps.
Note that the original PLL was capped at 600MHz/1.2gtps which was the Cyclone V over-clock-able limit.
Andrp19n:
Hello
Finally, I have compiled library in vhdl project. There were some issues with translating from sv to vhdl. However, I still couldn't launch the memory. Keep working on that. Thanks for help
uglyoldbob:
This controller seems great. I can get the existing demo projects to compile but am running into some problems integrating it into a vexriscv design using a wishbone bus.
Would anybody be willing to look at a demo of my project to help me figure out some compile errors I am getting?
Also, I noticed that the ddr3 DM signals are inout in the BrianHG_DDR3_PHY_SEQ_v16 module, but end up as just outputs in the sample projects when they go to the ddr3 dm pins.
I get a lot of messages like
--- Code: ---Error (13147): Input clock of DDIO node "BrianHG_DDR3_IO_PORT_ALTERA:BrianHG_DDR3_IO_PORT_ALTERA|altera_gpio_lite:DDR3_IO_DQS_inst[1].DDR3_IO_DQS_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|din_ddr" associated with DQS/DQ/DM pin is not driven by PHY Clock Buffer.
--- End code ---
https://home.uglyoldbob.com/firmware/altera-deca/test.zip
Edit: I figured out my problem. I'm building the system with litex and it was adding DM_PIN ON statements and things like "set_instance_assignment -name DQ_GROUP 9 -from ddram_dqs_p[1] -to ddram_dq[8]" which I removed. I also needed to drop the pll multiplier to 24 for the altera deca board.
BrianHG:
--- Quote from: uglyoldbob on October 14, 2024, 05:18:16 pm ---This controller seems great. I can get the existing demo projects to compile but am running into some problems integrating it into a vexriscv design using a wishbone bus.
Would anybody be willing to look at a demo of my project to help me figure out some compile errors I am getting?
Also, I noticed that the ddr3 DM signals are inout in the BrianHG_DDR3_PHY_SEQ_v16 module, but end up as just outputs in the sample projects when they go to the ddr3 dm pins.
I get a lot of messages like
--- Code: ---Error (13147): Input clock of DDIO node "BrianHG_DDR3_IO_PORT_ALTERA:BrianHG_DDR3_IO_PORT_ALTERA|altera_gpio_lite:DDR3_IO_DQS_inst[1].DDR3_IO_DQS_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|din_ddr" associated with DQS/DQ/DM pin is not driven by PHY Clock Buffer.
--- End code ---
https://home.uglyoldbob.com/firmware/altera-deca/test.zip
Edit: I figured out my problem. I'm building the system with litex and it was adding DM_PIN ON statements and things like "set_instance_assignment -name DQ_GROUP 9 -from ddram_dqs_p[1] -to ddram_dq[8]" which I removed. I also needed to drop the pll multiplier to 24 for the altera deca board.
--- End quote ---
To get my minimum DDR3 controller going, you first need to use this example file:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/main/BrianHG_DDR3_DECA_PHY_SEQ_only_v16/BrianHG_DDR3_DECA_test1_top.sv
You only need lines 247 thru 332, plus the parameters at the beginning.
For assigning the IO pins, you need the IO assignments in this file:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/main/BrianHG_DDR3_DECA_PHY_SEQ_only_v16/BrianHG_DDR3_DECA_test1_top.qsf
Lines 99 thru 199. (Assuming you have the same IO pins as the DECA board.)
In that same file, you also need lines 675 thru 681
In your .zip, in your 'terasic_deca.qsf' file, you should not have any:
--- Code: ---set_instance_assignment -comment "xxxxxx" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to xxxxxx[x]
or any
set_instance_assignment -name DQ_GROUP X -from xxxxxxxxx[X] -to xxxxxxxxxx[X]
--- End code ---
I guess the '-comment' means it is inactive.
But the '-name DQ_GROUP 9' is not used by my controller. Writing a DDR3 controller using these features would cap my design at 300MHz instead of the 400MHz which my controller can run at.
And you will also need match my DDR IO timing settings in your .sdc file:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/main/BrianHG_DDR3_DECA_PHY_SEQ_only_v16/BrianHG_DDR3_DECA.sdc
All entries, but, you will need to rename the pin labels to match your project.
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