Electronics > FPGA

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

<< < (75/75)

New PLL v1.4.
PLL now supports up to 1GHz for Arria V and Cyclone V, this means up to 2gtps.

Note that the original PLL was capped at 600MHz/1.2gtps which was the Cyclone V over-clock-able limit.

Finally, I have compiled library in vhdl project. There were some issues with translating from sv to vhdl. However, I still couldn't launch the memory. Keep working on that. Thanks for help


[0] Message Index

[*] Previous page

There was an error while thanking
Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod