Electronics > FPGA

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

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BrianHG:
New PLL v1.4.
PLL now supports up to 1GHz for Arria V and Cyclone V, this means up to 2gtps.

Note that the original PLL was capped at 600MHz/1.2gtps which was the Cyclone V over-clock-able limit.

Andrp19n:
Hello
Finally, I have compiled library in vhdl project. There were some issues with translating from sv to vhdl. However, I still couldn't launch the memory. Keep working on that. Thanks for help

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