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BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.50.

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BrianHG:
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*** NEW December 3, 2021.  BrianHG_DDR3_Controller V1.5 ***
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 :scared: A maddening over 11K lines of code....  :scared:
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A SystemVerilog DDR3 Memory Controller with up to 16 read/write ports with configurable width priority encoding.  Fully documented source code.

Simplified block diagram of BrianHG_DDR3_Controller V1.5:



(*** Just download the 'BrianHG_DDR3_README_V1.50.txt' and 'BrianHG_DDR3_README_V1.00.txt' for easy reading in a notepad. ***)

Note that the original v1.0 source files still exist, still function, and are backwards compatible, but understand that all the source files have been updated.  This includes the new .sdc files in the new demo projects.

In-depth instructions are located in the full v1.00 text release notes as well as all the parameters and ports are well documented within the source code and examples.


Written by Brian Guralnick.
For public use.
My GitHub repository release:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller

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BrianHG_DDR3_README_V1.00.txt Status/Revision Log, Instructions.
August 27, 2021.

Designed for Altera/Intel Quartus Cyclone V/10/MAX10 and others. (Unofficial Cyclone III & IV, may require overclocking.)
             Lattice ECP5/LFE5U series.  (Coming soon)
             Xilinx Artix 7 series.      (Coming soon)


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*** Release V1.00, August 27, 2021 **************************
*** Tested on Quartus Prime 20.1   **************************
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(Yes, 400MHz is official for -6 and 300MHz for -8 Cyclones/MAX10, -8 can be safely overclocked to 400MHz.)


--- Code: ---Featured full Quartus Prime 20.1 projects:  (Except for 'BrianHG_DDR3_CIII_GFX_FMAX_Test_Q13.0sp1')
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BrianHG_DDR3_DECA_GFX_DEMO                 400MHz, functional DDR3 System scrolling ellipse with optional RS232 debug port demo for Arrow DECA eval board.
BrianHG_DDR3_DECA_Show_1080p               400MHz, functional DDR3 System 1080p 32bit display with optional RS232 debug port demo for Arrow DECA eval board.
BrianHG_DDR3_DECA_RS232_DEBUG_TEST         400MHz, functional DDR3 System RS232 debug port demo for Arrow DECA eval board.
BrianHG_DDR3_DECA_only_PHY_SEQ             400MHz, functional DDR3 PHY Only controller with RS232 debug port demo for Arrow DECA eval board.
BrianHG_DDR3_CIV_GFX_FMAX_Test             400MHz, Hypothetical Cyclone IV DDR3 System scrolling ellipse build to verify FMAX.
BrianHG_DDR3_CIII_GFX_FMAX_Test_Q13.0sp1   400MHz, Hypothetical Cyclone III DDR3 System scrolling ellipse build to verify FMAX.  (Uses Quartus 13.0sp1)
BrianHG_DDR3_CV_GFX_FMAX_Fail              400MHz, Hypothetical Cyclone V-6 DDR3 System scrolling ellipse build to verify FMAX.  (FMAX FAILED)
BrianHG_DDR3_CV_GFX_FMAX_Test              300MHz, Hypothetical Cyclone V-6 DDR3 System scrolling ellipse build to verify FMAX.  (PASSED, but with features disabled)
BrianHG_DDR3_CV_PHY_ONLY_FMAX_Test         375MHz, Hypothetical Cyclone V-6 DDR3 PHY Only controller with RS232 debug port build to verify FMAX. (375MHz only, no multiport)
--- End code ---

Source Folders:
---------------
BrianHG_DDR3                               Source code for BrianHG_DDR3 controller.
BrianHG_DDR3_GFX_source                    Source code for rendering random ellipses with a scrolling screen.

Have the SystemVerilog source and can be simulated in Modelsim outside Quartus.


Screenshots folder:
-------------------
LC-LUT_screenshots/                        Contains tables of the compiled LC&LUT usage for various clock frequency and feature builds.
FMAX_screenshots/                          Contains FMAX timing analyzer results screenshots of various FPGA builds.

Check here for compiled FMAX & LC/LUT usage stats:
https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/msg3649318/#msg3649318

dmendesf:
Nice work. Is there a way to use it with VHDL under Quartus?

BrianHG:
Though I am not familiar with VHDL, I do know that in either Verilog or VHDL, you can initiate either code type module.

Just google: How do I instantiate a SystemVerilog module inside a VHDL design?

There has got to be good examples.  You just need to find out how to pass 2 dimentional arrays if you will be using my multi-port module unless you make a simple smaller verilog module with only the ports and settings you want shrinking what you call in your VHDL code.

If crossing code is vendor specific, maybe the best place to ask would be on Intel's forum.
I know Intel has instructions on how to insert VHDL code/modules into verilog source code.

ali_asadzadeh:
Thanks for sharing, Please make a reop on github too :-+ :-+ :-+

BrianHG:

--- Quote from: ali_asadzadeh on July 14, 2021, 06:46:41 am ---Thanks for sharing, Please make a reop on github too :-+ :-+ :-+

--- End quote ---
Coming in a few days once I fix the FMAX bottleneck.

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