Found it in UG331:
Using the LOCKED Signal
To operate properly, the DCM requires a stable, monotonic clock input. Once locked, the
DCM tolerates clock period variations up to the value specified in the specific FPGA data
sheet. If the input clock stays within the specified limits, then the output clocks always are
valid when the LOCKED output is High. However, it is possible for the clock to stray well
outside the limits, for the LOCKED output to stay High, and for the DCM outputs to be
invalid. It is good design practice to monitor both LOCKED and the STATUS signals.
Monitoring STATUS[1] is recommended as this will indicate when CLKIN has stopped
(moved outside the acceptable CLKIN tolerances). STATUS[1] will go High after one
missed CLKIN cycle. However, the DCM might not lose LOCKED unless CLKIN is
stopped for more than 100 ms. STATUS[1] is not a sticky bit; it will go Low once CLKIN has
returned. For the most robust indicator of the status of your DCM's output clock,
monitoring both the LOCKED and STATUS[1] bits is recommended.
So a short while after STATUS[1] is goes high, switch clocks before it unlocks.