Electronics > FPGA

Can Microchip Configurable Logic Block (CLB) match UART address?



I want to implement 1-Wire like slaves with a uC and looking for a option to stay sleeping while the master doesn't send the address.
Other functions like Search and Alert don't need to be implemented on sleep.
For this case I wonder if Microchip CLB would be able to match a preamble and address, even if 8 bits.

The specs are:
1x CLB - Interconnected fabric containing 32 Basic Logic Elements (BLE) / each BLE contains one 16-input Look-Up Table (LUT) and one flip-flop
4x CLC - Configurable Logic Cells - Integrated combinational and sequential logic

I have very limited experience in configurable circuits, so I wouldn't be surprised if the answer is trivial.


You'd need to keep the clock running so is there much benefit to being asleep?
What sort of baudrate are you looking at? - maybe you could decode in software & wake on a leasing edge - the RC osc would probably startfast enough for lower baudrates.

DS28E18 interface is powered from the 1-wire bus (saves your slave power) but you would need to wakeup mcu fairly quick, few microseconds.

Right. I ended up implementing it in assembly with the attiny. Need about 2MHz to do the proper shapes, so about 1mA per device when the bus is active (all need to be awake).

I was extending the 1W protocol with a industrial bus style mode (like CAN/Ethercat), where each device participates in the same 1W transaction and just sets some bits, so using the DS28E18 was not a option.


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