Electronics > FPGA

Cannot get data from BRAM IP


I tried to read data from a XILINX BRAM block by setting an address to `addrb` port, but it did not return the data. Can anyone help? I attached the timing and configurations of the BRAM IP.

What do you mean by "it did not return the data".
According to simulation pic you make three writes through port A. Definitely writing address 0 and address 2, and we can only guess the address 1, since is not readable without zooming into the waveform.
The port B only reads out changes done on address 0 and address 1. The changes at location 0 done through port A properly lags on port B output. And we don't know what did you write (if you wrote anything at all) at location 1, so it appears that the value read from the location 1 happens to be equal to the value written earlier to location 0.
At least zoom in to see addresses/values in each clock where the 'wea' signal is non-zero.


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