Electronics > FPGA

capture data from ADC with ISERDESE not working

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VAO1:
Yes, they are out of face coming from the ADC, but they must be aligned for entering the ISERDESE. That is why they are aligned inthe code. I attach a picture of the not aligned (blue) and aligned (green) signals. Yes they where rolling, because that signal is for the 14 bit ADC, and the ISERDESE input was with 6 bits (haslf of a 12 bit signal). Now what I do not understand really is how does a frame alignment algorythm works. I posted one that was passed to me, but cant really understand how it works. I understand there is a frame pattern, that when its meet, you can start sampling the iinput with no problem, but dont really get how it works. Any hint in this would be apreciated,maybe a reference where I could read about this (the implementation of it).
Thanks a lot for the answers

VAO1:
Good day,
starting from the beggining, the functioning of the ISERDESE. There is a thing I do not understand (maybe that should have been the first question). I have done a small program to just test the functioning of the ISERDESE. This progream just have an ISERDESE with the following definition:


--- Code: ---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;
entity Prueba_ISERDESE is
  Port (
  test_signal      : in std_logic;  --- seƱal para prueba del ISERDESE
  i_ADclk_p        : in std_logic;
  i_ADclk_n        : in std_logic;
  i_Lclk_p         : in std_logic;
  i_Lclk_n         : in std_logic;
  i_rst            : in std_logic; 
  salida : out std_logic_vector (7 downto 0)
  ); 
end Prueba_ISERDESE;

architecture Prueba_ISERDESE of Prueba_ISERDESE is

signal adclk_i : std_logic;
signal lclk_sys : std_logic;
signal not_lclk_sys : std_logic;
signal Lclk : std_logic;
signal Lclk_B : std_logic;
signal adclk : std_logic;

begin
    Lclk <= i_Lclk_p;
    Lclk_B <= i_Lclk_n;   
process (Lclk)
    begin
      if rising_edge(Lclk) then
          adclk <= i_ADclk_p;
      end if;
    end process;
-------------------------------   
bufio_lclk_sys : BUFIO port map (I => Lclk, O => lclk_sys) ;
not_lclk_sys <= not(lclk_sys);
------------------------------
bufr_ad_n : BUFR generic map(BUFR_DIVIDE => "1", SIM_DEVICE => "7SERIES") port map (I =>  (adclk), CE => '1',O => adclk_i,CLR => '0') ;   
-------------------------------   
iserdes_frame : ISERDESE2 generic map(
  DATA_WIDTH         => 7,                      --- 7
  DATA_RATE          => "SDR",     
  SERDES_MODE        => "MASTER",     
  --IOBDELAY        => "IFD",
  DYN_CLK_INV_EN    => "TRUE",             
  DYN_CLKDIV_INV_EN    => "FALSE",   
  INTERFACE_TYPE     => "NETWORKING")   
port map (                     
  D           => test_signal,                 
  DDLY         => '0',
  CE1         => '1',
  CE2         => '1',
  CLK         => lclk_sys,
  CLKB        => not_lclk_sys,
  RST         => i_rst,
  CLKDIV      => adclk_i,
  CLKDIVP      => '0',
  OCLK        => '0',
  OCLKB        => '0',
  DYNCLKSEL        => '0',
  DYNCLKDIVSEL      => '0',
  SHIFTIN1     => '0',
  SHIFTIN2     => '0',
  BITSLIP     => '0',                         
  O       => open,
  Q8        => salida(7),
  Q7        => salida(6),
  Q6        => salida(5),
  Q5        => salida(4),
  Q4        => salida(3),
  Q3        => salida(2),
  Q2        => salida(1),
  Q1        => salida(0),
  OFB       => '0',
  SHIFTOUT1    => open,
  SHIFTOUT2     => open);

end Prueba_ISERDESE;

--- End code ---
The waveforms of this is in the attached picture.
As I understand, the output from the ISERDESE happens in the next rising edge of CLKDIV, but in the attached picture, it is happening in 2 "stages", first bits 0 and 2, and then the rest of the bits. Also, because of the definition (DATA_WIDTH = 7), shouldnt the bit 0 be neglected (because the ISERDES fills first the Q( 8 ) output).
Thanks a lot in advance.

Rainwater:
Thanks for the code tags.
 your trace do not show all the clocks and from other forms, the most approved solution has beed a proper phase relationship between them. Some chips even requiring a calibration period.
Maybe try setting the testbench to slowly alter the phase until the traces match the datasheet?
Another possibility 8s the data may need to be encoded with 8B/10B or similar. Im just a beginner myself, good luck

nctnico:
Maybe this is a simulation issue. I see the inverted clock is being made from an assignment / equation. Some simulators don't look at a signal until the next transistion of the source signal and thus cause a delay of 1 clock cycle. To take this effect out of the equation, make all clocks in the test bench and don't have any assignments from one clock signal to another where it comes to clocks at any place in the code.

From my experience with GHDL this won't work properly when simulated:

--- Code: ---Lclk <= i_Lclk_p;
Lclk_B <= i_Lclk_n;   
not_lclk_sys <= not(lclk_sys);

--- End code ---

VAO1:
Good day. I have tryed to change the inverted inputs to an input from the simulation but didnt change. I have done some tests, which I attach as pictures. There are 2 tests that where done: first, a pulse with different widths was entered to the ISERDES at the same moments (in different simulations), with its respective CLK, CLKDIV and RESET signals (the reset and CLKDIV signals are in phace).
A second test was done where a the same width pulse was entered at different times, also CLK, CLKDIV and RESET signals (the reset and CLKDIV signals are in phace).
From the first test (can be seen in the pictures), what I do not understand is the followinmg:
1) Why does in the first test pulse, Test pulse = 1,5[ns], the bit that gets set is the Q1 bit (from the ISERDESE), shouldnt it be bit Q8 (as the document UG471 states). The reset signal and the CLKDIV signals are in phase so the first bit should be (as my understanding) Q8.
2) When the test pulse is = 4,5 [ns] and bigger, some outputs start from 2 CLKDIV rising edge pulses. Shouldnt they all be after one CLKDIV rising edge (as stated in the datasheet).

From the second test it can be seen that when the test pulse is in the 2nd CLK rising 3dge, 2 output bits are set, why does this happen?.

Thanks a lot in advance.

PS: this is the codefor the ISERDESE:


--- Code: ---iserdes_frame : ISERDESE2 generic map(
  DATA_WIDTH         => 7,                      --- 7
  DATA_RATE          => "SDR",     
  SERDES_MODE        => "MASTER",     
  --IOBDELAY        => "IFD",
  DYN_CLK_INV_EN    => "TRUE",                  --- TRUE             
  DYN_CLKDIV_INV_EN    => "FALSE",   
  INTERFACE_TYPE     => "NETWORKING")   
port map (                     
  D           => test_signal,                   --- i_adclk_p
  DDLY         => '0',
  CE1         => '1',
  CE2         => '1',
  CLK         => lclk_sys,
  CLKB        => not_lclk_sys,
  RST         => i_rst,
  CLKDIV      => adclk_i,
  CLKDIVP      => '0',
  OCLK        => '0',
  OCLKB        => '0',
  DYNCLKSEL        => '0',
  DYNCLKDIVSEL      => '0',
  SHIFTIN1     => '0',
  SHIFTIN2     => '0',
  BITSLIP     => '0',                         -- bitslip_odd
  O       => open,
  Q8        => salida(7),
  Q7        => salida(6),
  Q6        => salida(5),
  Q5        => salida(4),
  Q4        => salida(3),
  Q3        => salida(2),
  Q2        => salida(1),
  Q1        => salida(0),
  OFB       => '0',
  SHIFTOUT1    => open,
  SHIFTOUT2     => open);
end Prueba_ISERDESE;

--- End code ---

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