Electronics > FPGA

capture data from ADC with ISERDESE not working

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Good day.
I need to acquire the data coming from an 12 bit ADC, which has 8 LVDS outputs, one frame clock, and one bit clock. To do this, I am basing the design in the XAPP524 document from Xilinx. To do this, first I am deserialising the frame clock using an ISERDESE2. For this deserialization, the ISERDESE uses as input the positive part of the frame clock, as CLK clock the bit clock, and  as CLDIV clock an aligned version of the frame clock with the bit clock (As stated in document UG471), also it has a bitslip signal, but not using that yet.
The problem is that the output of the ISERDESE2 keeps changing, but the signal being input to it is allways the same, and dont really now why this is.
I attach a picture of the waveforms, where i_rst is the reset signal, I-ADCLK_94_p_0 is the input signal (to D pin in ISERDESE), LCLK is the bit clock, adclk is the aligned with bit clock version of the frame clock (input to CLKDIV of Iserdese) and frame_para_odd[7:0] is the output of the ISERDESE.
Any help would be apreciated, because dont really now why this is hapening.
Thanks a lot in advance.

Is adclk suppose to be 50% duty cycle b/c it is 4high 3 low

which ADC?

Good day, Thank you for your answers
The ADC corresponds to the ADS5294. Its 4 up and 3 down because of the datasheet waveform (its 14 bits, I attach a picture).
Also, for the frame discovery machine (to synchronize the incoming data with the FPGA), I do not really understand how does it work. I have a code thats working (that was passed to me), but dont really understand how does it work (I also attach the code and the part of the code (ISERDESE) that makes the frame alignment). This works with a 12 bit word, so how could this be changed for a 14 bit word??, just changing the D value in the ISERDESE??
Thanks a lot in advance.

I haven't checked all the timing diagrams, but the one you posted and several others in the datasheet show the clocks out of phase with each other. Your trace is difficult to see, but looks as tho the clocks are in phase. The reoccurring data pattern is very strange comming from a real device. If the values where approximately the same, it would make sense, but being so different and repeating, it's either interlaced data or an accumulated error rolling over.


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