Digital, Java rtl sim, with vhdl and verilog support (educational only)

[DiTBho]

"Digital" is an easy-to-use digital logic designer and circuit simulator designed for educational purposes.
It's on github, see here.

I've been using it for a couple of days, and for me, I have to say that for simple projects it works well and allows you to integrate external files written in vhdl (or verilog), using iterative objects such as buttons, leds, hex displays (4bit), which is nice and very handy!

However, the vhdl simulation part has some issues with signals, and it's not easy to get timing diagrams, neither it's possible to comfortably use "vhdl packages" among files.

It's much more enjoyable with logic gates and then to export "HDL code" than writing HDL code.
Anyway, I'm reporting it, because it's worth it 

[DiTBho]

(I'm using it to prepare a live demo.
I could do it another way,
but I want to evaluate all the alternatives)

[DiTBho]

(umm, exporting to png ... doesn't correctly work
I cannot attach a decent snapshot of what I am doing)

[c64]

Interesting ...
They support VHDL and Verilog, and can output into JEDEC file for GAL16v8 or GAL22v10.

[DiTBho]

One of the things I do find annoying with Digital is that vhdl-blocks(1)

• do not support packages
• support records internally to a block, but not outside

This makes more difficult to write complex projects.

Code: [Select]

.____________                           ___________
|            |                         |           |
|   record   |     std_logic_vector    |  record   |
|      +------------------------------------>      |
|____________|                         |___________|


Since Vhdl does neither support "C-casting" nor "C-union", and since vhdl-blocks in Digital only support "std_logic_vector", you have to "serialize" a Vhdl-record into std_logic_vector, then you can wire two blocks, and then you have to "deserialize" std_logic_vector into record.


(1) in Digital, in order to use Vhdl you have to use a "Vhdl-block", which points to an external Vhdl file.
Vhdl-blocks can be connected with wires, wire can be std_logic (1bit) or std_logic vector (n-bit).

[DiTBho]

I wish there was something similar but written in C and using { Moitf, GTK*, QT*, ... } graphic libraries.
Java is OK, but ... well, not ideal, and I cannot have a JRE on { HPPA, MIPS32, MIPS4, POWER10, ... }