Author Topic: How to pipeline DSP48 input?  (Read 3620 times)

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Offline notoothTopic starter

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How to pipeline DSP48 input?
« on: September 18, 2023, 11:02:05 pm »
I got this warning in Vivado. Can anyone tell me how to fix?
Quote
DPIP #1 DSP design_1_i/add_tlast/inst/sa_tlast_out1 input design_1_i/add_tlast/inst/sa_tlast_out1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
 

Offline asmi

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Re: How to pipeline DSP48 input?
« Reply #1 on: September 18, 2023, 11:31:19 pm »
Add pipeline registers in front of/to the output of DSP?

Offline notoothTopic starter

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Re: How to pipeline DSP48 input?
« Reply #2 on: September 18, 2023, 11:37:09 pm »
Yes, I think so.
 

Offline hamster_nz

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Re: How to pipeline DSP48 input?
« Reply #3 on: September 19, 2023, 12:01:16 am »
If the design meets timing, then don't bother.

Otherwise add a set of pipelining registers to what is being multiplied, and cross fingers that the tools match the pattern and pull the pipelining registers into the DSP block.
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline notoothTopic starter

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Re: How to pipeline DSP48 input?
« Reply #4 on: September 19, 2023, 12:12:12 am »
The design failed timing. Can you send me a tutorial or an example of non-pipelining registers and pipelining registers?
« Last Edit: September 19, 2023, 12:14:31 am by notooth »
 

Offline hamster_nz

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Re: How to pipeline DSP48 input?
« Reply #5 on: September 19, 2023, 02:10:09 am »
You might find useful examples in "Vivado Design Suite User Guide Synthesis" or maybe "XST User Guide for Virtex-6,
Spartan-6, and 7 Series Devices"

https://docs.xilinx.com/v/u/2017.4-English/ug901-vivado-synthesis

https://docs.xilinx.com/v/u/en-US/xst_v6s6

But the shortest explanation is to store the inputs for the multiplication in registers, and then use the contents of the registers for the multiply.

Code: [Select]
process(clk)
    begin
        if rising_edge(clk) then
            result <= regA * RegB;
            -- Input registers
            regA <= inputA
            regB <= inputB;
        end if;
    end if;
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline notoothTopic starter

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Re: How to pipeline DSP48 input?
« Reply #6 on: September 19, 2023, 02:39:58 am »
There is no multiplication in my module:

Code: [Select]
module add_tlast (
     output reg sa_tlast_out = 0
    ,input      aclk
    );

always @(posedge aclk) begin
sa_tlast_out = 1;
end

endmodule
 

Offline hamster_nz

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Re: How to pipeline DSP48 input?
« Reply #7 on: September 19, 2023, 05:57:11 am »
Perhaps then the multiplier is in a different module?
The one that uses this module's output?
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline hamster_nz

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Re: How to pipeline DSP48 input?
« Reply #8 on: September 19, 2023, 06:40:54 am »
Oh, also note: IIRC you can't have an initial value for the DSP48 interal registers. If you do set an initial value it will prevent the register from being pushed into the DSP block.
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 


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