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DPIP #1 DSP design_1_i/add_tlast/inst/sa_tlast_out1 input design_1_i/add_tlast/inst/sa_tlast_out1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
process(clk) begin if rising_edge(clk) then result <= regA * RegB; -- Input registers regA <= inputA regB <= inputB; end if; end if;
module add_tlast ( output reg sa_tlast_out = 0 ,input aclk );always @(posedge aclk) begin sa_tlast_out = 1;endendmodule