The Cheapest FPGA Development Board?

[Toney]

I was trying to buy a Lattice MachXO3D breakout board, but unfortunately they ran out. Now the price for the development boards has tripled. It was a great looking board that only cost ~16$.

Is there something similar by other manufacturers? I need the board for converting a 88.2kHz, 32 bit audio stream with separate left, right, clock and channel streams to SPIDF (at least 88.2 kHz, 24 bits, preferably with capacity for 192kHz). This does not require much resources, all current FPGAs are probably capable enough, if not an overkill. However, the clock has to be multiplied, so a PLL with preferably x4 capability is preferred, and there needs to be at least four inputs and an output. I would like to mount the SPIDF output direct to the board so this requires some space for few resistors also to get the output to the correct range.



Are there any boards you would suggest?

[langwadt]

I was trying to buy a Lattice MachXO3D breakout board, but unfortunately they ran out. Now the price for the development boards has tripled. It was a great looking board that only cost ~16$.

Is there something similar by other manufacturers? I need the board for converting a 88.2kHz, 32 bit audio stream with separate left, right, clock and channel streams to SPIDF (at least 88.2 kHz, 24 bits, preferably with capacity for 192kHz). This does not require much resources, all current FPGAs are probably capable enough, if not an overkill. However, the clock has to be multiplied, so a PLL with preferably x4 capability is preferred, and there needs to be at least four inputs and an output. I would like to mount the SPIDF output direct to the board so this requires some space for few resistors also to get the output to the correct range.



Are there any boards you would suggest?

QMTECH Xilinx FPGA Spartan6 XC6SLX16  is about that price on aliexpress

[Toney]

I was trying to buy a Lattice MachXO3D breakout board, but unfortunately they ran out. Now the price for the development boards has tripled. It was a great looking board that only cost ~16$.

Is there something similar by other manufacturers? I need the board for converting a 88.2kHz, 32 bit audio stream with separate left, right, clock and channel streams to SPIDF (at least 88.2 kHz, 24 bits, preferably with capacity for 192kHz). This does not require much resources, all current FPGAs are probably capable enough, if not an overkill. However, the clock has to be multiplied, so a PLL with preferably x4 capability is preferred, and there needs to be at least four inputs and an output. I would like to mount the SPIDF output direct to the board so this requires some space for few resistors also to get the output to the correct range.



Are there any boards you would suggest?

QMTECH Xilinx FPGA Spartan6 XC6SLX16  is about that price on aliexpress

Thank you for the suggestion.

Do I recall correctly that Xilinx boards require a programmer though?

[langwadt]

I was trying to buy a Lattice MachXO3D breakout board, but unfortunately they ran out. Now the price for the development boards has tripled. It was a great looking board that only cost ~16$.

Is there something similar by other manufacturers? I need the board for converting a 88.2kHz, 32 bit audio stream with separate left, right, clock and channel streams to SPIDF (at least 88.2 kHz, 24 bits, preferably with capacity for 192kHz). This does not require much resources, all current FPGAs are probably capable enough, if not an overkill. However, the clock has to be multiplied, so a PLL with preferably x4 capability is preferred, and there needs to be at least four inputs and an output. I would like to mount the SPIDF output direct to the board so this requires some space for few resistors also to get the output to the correct range.



Are there any boards you would suggest?

QMTECH Xilinx FPGA Spartan6 XC6SLX16  is about that price on aliexpress

Thank you for the suggestion.

Do I recall correctly that Xilinx boards require a programmer though?

yes, a Xilinx programming cable (clone) is about the same as a board

[Canis Dirus Leidy]

Another variant: EP4CE15 core board from QMTech ($19 without shipping) plus ChinaBlaster programmer (approx. $3 or $4).

[Toney]

Another variant: EP4CE15 core board from QMTech ($19 without shipping) plus ChinaBlaster programmer (approx. $3 or $4).

Thank you, I will check it out in more detail.

I forgot to say, the board should be able to be powered without an adapter or USB, direct from a PSU.

[SiliconWizard]

QMTECH boards are typically powered externally. (Power jack.)

But given your project, I would also suggest  an Upduino (iCE40 UP).
https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/

Probably more than enough for what you described, and includes the programmer.

[Toney]

QMTECH boards are typically powered externally. (Power jack.)

But given your project, I would also suggest  an Upduino (iCE40 UP).
https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/

Probably more than enough for what you described, and includes the programmer.

One more excellent suggestion. Smaller is certainly better, the only thing I am a bit worried about is whether the SPIDF connectors (optical/RCA) will fit on the board. For reference here is the RCA connector, optical transmitter is probably approximately similar sized, I am not sure yet which I will mount.

[langwadt]

if you are feeling adventurous, https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html

[Toney]

if you are feeling adventurous, https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html

Yes, I saw this one, the price quite likely can't be beat. Unfortunately, it's USB power only as I understand. Also, the documentation that I found was non-existent, which may cause a lot of trouble.

[langwadt]

if you are feeling adventurous, https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html

Yes, I saw this one, the price quite likely can't be beat. Unfortunately, it's USB power only as I understand. Also, the documentation that I found was non-existent, which may cause a lot of trouble.

you can power if from a psu, as long as it is 5V

[Toney]

if you are feeling adventurous, https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html

Yes, I saw this one, the price quite likely can't be beat. Unfortunately, it's USB power only as I understand. Also, the documentation that I found was non-existent, which may cause a lot of trouble.

you can power if from a psu, as long as it is 5V

This is why the lack of documentation may be a problem. At a price cheaper than a hamburger I still almost want to dare.

[BrianHG]

And unless you know quite a bit about digital filters (at least understanding z domain, sampling theory, FIR filters, IIR filters, polyphase filters, dithering, sigma delta, etc.), this would be a long journey.

He need not go that high quality, however, even quality linear and cubic interpolation still require a number of multiply-add modules.  Also, for the higher domain filters, make sure you have access to floating point multiply-add-divide as well some trig and root functions.

Thankfully, Intel finally opened up all these floating point functions for free in Quartus.  A decade ago, we had to pay for many of these as well as more of the advanced ones.  Even the basic FIR filter compiler is now available for free.

[Foxxz]

Excuse my ignorance on the subject. Going from 32bit audio to 24bits should be easy by just dropping the 8 LSBs. Optionally use them to decide if you want to round up the remaining MSBs.

Going from 88.2khz to 192khz is going to be more difficult.
192khz / 88.2khz = 2.176870748
2 * 88.2khz = 176.4khz
192khz - 176.4khz = 15.6khz
1s / 15600hz = 0.000064103s

So I would start by sending every sample twice. And then do the calculation to slip in an extra third sample every 0.000064103 seconds. Should be easy to figure out based on your clock speed.

Its not an upconversion. It won't make your audio sound any better like some of the more complicated schemes proposed by others might. Its mainly just a format conversion.

[langwadt]

if you are feeling adventurous, https://www.seeedstudio.com/Sipeed-Tang-Nano-FPGA-board-powered-by-GW1N-1-FPGA-p-4304.html

Yes, I saw this one, the price quite likely can't be beat. Unfortunately, it's USB power only as I understand. Also, the documentation that I found was non-existent, which may cause a lot of trouble.

you can power if from a psu, as long as it is 5V

This is why the lack of documentation may be a problem. At a price cheaper than a hamburger I still almost want to dare.

there's a datasheet on that page with pinout showing two 5V pins

[Foxxz]

Excuse my ignorance on the subject. Going from 32bit audio to 24bits should be easy by just dropping the 8 LSBs.

Optionally use them to decide if you want to round up the remaining MSBs.

That's sigma delta modulation in a nutshell, extremely simplified.

So I would start by sending every sample twice.

You just injected a ton of harmonics. Interpolation is easy, getting rid of the unwanted spectrum is the tricky part that needs tons of computation.

Could you point me to a reference on the subject? I know DACs can be a tad more complicated but when I think of a DAC playing a low sample rate VS a DAC playing a high sample rate the low sample rate is simply holding the voltage at the specified level for a longer period of time.

[langwadt]

Excuse my ignorance on the subject. Going from 32bit audio to 24bits should be easy by just dropping the 8 LSBs.

Optionally use them to decide if you want to round up the remaining MSBs.

That's sigma delta modulation in a nutshell, extremely simplified.

So I would start by sending every sample twice.

You just injected a ton of harmonics. Interpolation is easy, getting rid of the unwanted spectrum is the tricky part that needs tons of computation.

Could you point me to a reference on the subject? I know DACs can be a tad more complicated but when I think of a DAC playing a low sample rate VS a DAC playing a high sample rate the low sample rate is simply holding the voltage at the specified level for a longer period of time.

holding the voltage at a specific level for a sample period (zero-order hold) is  part of how the DAC (usually) works

there's no DAC involved as long as you are just massaging numbers, you have discrete values at discrete times

this has a very brief intro:  https://homes.esat.kuleuven.be/~maapc/static/files/SYSTHEORY/Slides/Lecture13/Lecture13-Discretization%20and%20reconstruction%20of%20signals.pdf

[BrianHG]

Excuse my ignorance on the subject. Going from 32bit audio to 24bits should be easy by just dropping the 8 LSBs.

Optionally use them to decide if you want to round up the remaining MSBs.

That's sigma delta modulation in a nutshell, extremely simplified.

So I would start by sending every sample twice.

You just injected a ton of harmonics. Interpolation is easy, getting rid of the unwanted spectrum is the tricky part that needs tons of computation.

     With Foxxz's comment, it sounds like simple resampling + a tuned low pass filter would be enough for him.  This is not absolute junk, but it's a beginner's step and a properly tuned low pass filter will reject a chunk of the nasty band.  Higher quality output filters would just begin to mimic existing DAC output analog reconstruction filters.

     Unfortunately, even a 1.50$ 32bit stereo audio DAC from TI has a higher quality internal up-sampling when it takes in 16/24/32 bit 44.1KHz source and up-samples the source data internally driving it's dac at 384KHz.  This price-to-up-sampling quality will not be matched on a 1$ FPGA, not to mention the needed bootprom, 32bit DAC and powersupply which doesn't exist for anything less than at least 10$.

     This project should be taken as a FPGA learning experience and you should attempt to at least match the up-sampling quality of the bottom end TI DAC's internal one.  This means full processing as blueskull has been touting and this also means an FPGA with some good strong core capabilities + a lot of work.

     If you want just the up-sampling quality, there are components much cheaper and all the mathematics have already been done.  If you want the learning experience, go with the FPGA and make sure you can have some PC connectivity to sniff the data & set some controls.  IE, at lease make sure your FPGA board has at least and additional USB/RS232 interface.

[Toney]

I need the board for converting a 88.2kHz, 32 bit audio stream with separate left, right, clock and channel streams to SPIDF (at least 88.2 kHz, 24 bits, preferably with capacity for 192kHz).

To convert between sample rates and bit depths, you need to perform sample rate conversion (for sample rates) and dithering/sigma delta modulation (for bit depth).

Fraction ratio sample rate converter (or ASRC to an extend) with good quality consumes A LOT OF COMPUTATIONAL POWER.

This is anything but a simple logic conversion. There are a lot of math behind it, and that maps to a lot of MACs (multiplications and additions) per second needed.

You'd want an FPGA with hardware multipliers, preferably MACs.

And unless you know quite a bit about digital filters (at least understanding z domain, sampling theory, FIR filters, IIR filters, polyphase filters, dithering, sigma delta, etc.), this would be a long journey.

I am not changing the sample rate, it's a simpler format conversion from some ancient I2Sish (in spirit) standard to SPIDF. The clock is multiplied since the clock for SPIDF needs to be faster as there are two channels.

[BrianHG]

I need the board for converting a 88.2kHz, 32 bit audio stream with separate left, right, clock and channel streams to SPIDF (at least 88.2 kHz, 24 bits, preferably with capacity for 192kHz).

To convert between sample rates and bit depths, you need to perform sample rate conversion (for sample rates) and dithering/sigma delta modulation (for bit depth).

Fraction ratio sample rate converter (or ASRC to an extend) with good quality consumes A LOT OF COMPUTATIONAL POWER.

This is anything but a simple logic conversion. There are a lot of math behind it, and that maps to a lot of MACs (multiplications and additions) per second needed.

You'd want an FPGA with hardware multipliers, preferably MACs.

And unless you know quite a bit about digital filters (at least understanding z domain, sampling theory, FIR filters, IIR filters, polyphase filters, dithering, sigma delta, etc.), this would be a long journey.

I am not changing the sample rate, it's a simpler format conversion from some ancient I2Sish (in spirit) standard to SPIDF. The clock is multiplied since the clock for SPIDF needs to be faster as there are two channels.

If you plan on making a PCB for this in the future, and all you want to do is format conversion, an Intel MAX10 fpga is useful.  You get 2 PLLs for increasing the source clock frequency (you will still need a trick or 2 to lift up a ~1MHz clock to the internal FPGA's minimum PLL 10MHz clock, but this can be done with a local crystal oscillator and using both PLLs), and the FPGA operates without a bootprom and only requires 1 single supply 3.3v.  It's available in QFP 144pin or smaller 32pin BGA.  They are not the cheapest at ~7$ each and overkill for your app.

[Toney]

I am not changing the sample rate, it's a simpler format conversion from some ancient I2Sish (in spirit) standard to SPIDF. The clock is multiplied since the clock for SPIDF needs to be faster as there are two channels.

How much jitter can you live with on the output? If your receiver can tolerate a crazy amount of jitter, just use a high clock (say, at least 4x the input clock and 2x the output clock) and miss clock pulses from time to time instead of using a PLL. Then this would fit easily within 1K LUT, which is within the capability of that Lichee Tang Nano board.

IIRC, the jitter is not too much if it is within quarter of the unit interval. However, even at 88.2 kHz the clock needs to run at 88200*32*2*2 = 11.2 mHz. I believe on that board the crystal is not fast enough for the trick. What is the problem with using a PLL?

Below is the code, where I assume having access to a double rate clock. Even then, SPIDF runs at double the rate by default because of the biphase-mark encoding and there are two channels, so the clock is four times faster (and if I wanted to get it to double that then 8x). However, it is possible to also use both the up and down tick of the clock, halving the requirement. Whether this actually works in practice is a other question, but the code below is implemented this way, it is assumed Clock2 runs at twice the frequency of Clock1 (the retrieved clock - which runs at ~3mHz).

module SPIDF(
    input Clock1,
    input Clock2,
    input DataL,
    input DataR,
    input wClock,
    inout SPIDF
    );



reg [1:0] Buffer [0:63][0:1];

reg sw1 = 0;
reg sw2 = 0;
reg sw3 = 0;
reg sw4 = 0;
reg sw5 = 0;
reg sw6 = 0;
reg sw7 = 0;

reg initialsw = 0;
reg preamblesw = 0;
reg channelsw = 0;
reg lastbit = 0;
reg SPIDFOut = 0;
reg paritybit = 0;

reg [5:0] k = 0;
reg [5:0] h = 0;
reg [9:0] n = 0;
reg [2:0] z1 = 0;
reg [4:0] z2 = 0;
reg [5:0] offset = 40;

reg [7:0] B0;
reg [7:0] B1;
reg [7:0] M0;
reg [7:0] M1;
reg [7:0] W0;
reg [7:0] W1;

wire DL = DataL;
wire DR = DataR;

reg sw0 = 0;

always @(posedge wClock) begin
sw0=1;
end

always @(negedge wClock) begin
if (sw0==1) begin
sw1 = 1;
end
end

always @(posedge Clock1) begin
if (sw3==0) begin
   if (sw1==1) begin //Delay 14
      k=k+1;
      if (k==15) begin
         sw2 = 1;
      end
      if (k==37) begin
         sw3 = 1;
      end
   end
end

if (sw2==1) begin
   Buffer[63-h][0] = DL;
   Buffer[63-h][1] = DR;
   h=h+1;
end
end

always @(negedge Clock2, posedge Clock2) begin
if (sw3==1) begin
   if(preamblesw==0) begin
      if(initialsw==0) begin
         if(lastbit==0) begin
            SPIDFOut = B0[z1];
         end
         else begin
            SPIDFOut = B1[z1];
         end
      end
      else if(channelsw==0) begin
         if(lastbit==0) begin
            SPIDFOut = M0[z1];
         end
         else begin
            SPIDFOut = M1[z1];
         end
      end   
      else begin //Channel=1
         if(lastbit==0) begin
            SPIDFOut = W0[z1];
         end
         else begin
            SPIDFOut = W1[z1];
         end
      end
      z1=z1+1;
      if (z1==0) begin
         preamblesw=1;
         initialsw=1;
      end
   end
   else begin
      if (z2<24) begin //Data bits (LSB first, 2's complement).
         if (Buffer[z2+offset][channelsw]==0) begin
            if (sw6==0) begin
               SPIDFOut = 1-SPIDFOut;
            end
         end
         else begin
            SPIDFOut = 1-SPIDFOut;
            if (sw6==0) begin
               paritybit = 1-paritybit;
            end
         end
      end
      
      else if (z2==24) begin  //Validity bit, 0 = valid bit, 1 = invalid.
         if (sw6==0) begin //Set to 0
               SPIDFOut = 1-SPIDFOut;
         end
      end
      
      else if (z2==25) begin //subcode / user data
         if (sw6==0) begin //Set to 0.
               SPIDFOut = 1-SPIDFOut;
         end
      end
      
      else if (z2==26) begin //channel status according to AES3.
         if (n==1) begin //0100 = 88.2kHz
            SPIDFOut = 1-SPIDFOut;
            if (sw6==0) begin
               paritybit = 1-paritybit;
            end
         end
         else begin
            if (sw6==0) begin
               SPIDFOut = 1-SPIDFOut;
         end
         end
      end
      
      else begin //set even parity
         if (paritybit==0) begin
            if (sw6==0) begin //Set to 0.
               SPIDFOut = 1-SPIDFOut;
            end
         end
         else begin
            SPIDFOut = 1-SPIDFOut;
         end
      end
      if (sw6==1) begin
         z2=z2+1;
         if (z2==28) begin
            z2=0;
         end
         if (z2==0) begin
            if (channelsw==1) begin
               sw7=1-sw7;
               n=n+1;
            end
            if (sw7==0) begin
               offset=40;
            end
            else begin
               offset=8;
            end
            channelsw=1-channelsw;
            preamblesw=1-preamblesw;
            lastbit=SPIDFOut;
            paritybit=0;
            if (n==192) begin
               n=0;
               initialsw=0;
            end
         end
      end
      sw6=1-sw6;
   end
end   
   

end

assign SPIDF = SPIDFOut;


integer i;
initial begin
for (i=0;i<32;i=i+1) begin
   Buffer[0]=0;
   Buffer[1]=0;
end
B0=8'b00010111;
B1=8'b11101000;
M0=8'b01000111;
M1=8'b10111000;
W0=8'b00100111;
W1=8'b11011000;
end
endmodule

[BrianHG]

Do you have access to the CPU's clock generating the I2S signal.  This may be at a higher frequency, then all you need to do is divide.
Not every FPGA has a PLL.
Altera/Intel FPGA's internal PLLs need at least a 5MHz source clock to function within spec.  Output can be as high as ~750MHz.   With trickery, you can run them with a source clock lower than 5MHz.

[Toney]

Do you have access to the CPU's clock generating the I2S signal.  This may be at a higher frequency, then all you need to do is divide.
Not every FPGA has a PLL.
Altera/Intel FPGA's internal PLLs need at least a 5MHz source clock to function within spec.  Output can be as high as ~750MHz.   With trickery, you can run them with a source clock lower than 5MHz.

No, unfortunately. The ~3 MHz (88200*32) clock needs to be multiplied.

[BrianHG]

Do you have access to the CPU's clock generating the I2S signal.  This may be at a higher frequency, then all you need to do is divide.
Not every FPGA has a PLL.
Altera/Intel FPGA's internal PLLs need at least a 5MHz source clock to function within spec.  Output can be as high as ~750MHz.   With trickery, you can run them with a source clock lower than 5MHz.

No, unfortunately. The ~3 MHz (88200*32) clock needs to be multiplied.

Find an FPGA with a PLL which can start as low as 3MHz.  Or, use an XOR gate (can be one inside the FPGA) with an LC delay line from 1 input to the next to double your source 3MHz to 6MHz.  (Note, without re-PLLing the 6MHz output of the XOR gate, that 6MHz won't have a nice 50/50 duty cycle unless the LC delay line has dead perfect tuning.)

[Toney]

Do you have access to the CPU's clock generating the I2S signal.  This may be at a higher frequency, then all you need to do is divide.
Not every FPGA has a PLL.
Altera/Intel FPGA's internal PLLs need at least a 5MHz source clock to function within spec.  Output can be as high as ~750MHz.   With trickery, you can run them with a source clock lower than 5MHz.

No, unfortunately. The ~3 MHz (88200*32) clock needs to be multiplied.

Find an FPGA with a PLL which can start as low as 3MHz.  Or, use an XOR gate (can be one inside the FPGA) with an LC delay line from 1 input to the next to double your source 3MHz to 6MHz.  (Note, without re-PLLing the 6MHz output of the XOR gate, that 6MHz won't have a nice 50/50 duty cycle unless the LC delay line has dead perfect tuning.)

So the clock is 2.82MHz. Turns out the $5 FPGA has the low limit of 3MHz, do you recon it will work mildly out of spec?

https://alcom.be/wp-content/uploads/2018/09/GOWIN_100918_DS100-1.2E_GW1N-series-of-FPGA-Products-Data-Sheet-1.pdf