The Cheapest FPGA Development Board?

[BrianHG]

Sorry, I never used Gowin.
The limitation is usually set by the compiler & trying to trick the Compiler/FPGA can lead to PLL instability.

[Foxxz]

Thank you to everyone that took the time to explain the nuances of resampling, etc. That was helpful to know.

[radiolistener]

Excuse my ignorance on the subject. Going from 32bit audio to 24bits should be easy by just dropping the 8 LSBs.

These 8 LSB bits contains significant information which will be required for better quality upsampling from 88.2 to 192 kHz. These bits contains important information required for good signal reconstruction at higher sample rate.

So I would start by sending every sample twice. And then do the calculation to slip in an extra third sample every 0.000064103 seconds. Should be easy to figure out based on your clock speed.

Upsampling requires interpolation, if you just copy previous sample, you will have bullshit sound. And interpolation should use all 32 bits of original stream on the input.

At a glance, there is needs upsample interpolation from 88.2 kHz to 28224 kHz and then downsample to 192 kHz.

[Toney]

Excuse my ignorance on the subject. Going from 32bit audio to 24bits should be easy by just dropping the 8 LSBs.

Optionally use them to decide if you want to round up the remaining MSBs.

That's sigma delta modulation in a nutshell, extremely simplified.

So I would start by sending every sample twice.

You just injected a ton of harmonics. Interpolation is easy, getting rid of the unwanted spectrum is the tricky part that needs tons of computation.

Could you point me to a reference on the subject? I know DACs can be a tad more complicated but when I think of a DAC playing a low sample rate VS a DAC playing a high sample rate the low sample rate is simply holding the voltage at the specified level for a longer period of time.

Check out the sampling theorem. Convolving by sinc functions gives mathematically "perfect" reconstruction (IE. with the same Fourier transform up to the prior Nyquist frequency and then all zeroes). So a sinc of n points is the usual choice for good quality interpolation - very expensive of course - and also not causal. A spline of four points can also be used, and linear interpolation works for 2 points. You can google the effect on Fourier transform of these, it's not very good.

Holding points for two samples seems the same as convolving by a rectangle - which is how digital already works. As such yes the rate is faster, but now you have the mirroring of frequencies from the Nyquiest so the low pass filtering would still be needed (and indeed the sinc interpolation is a perfect low pass filter).

The above is only the starting point, I am sure engineers have developed interpolation methods that work better in practice.

[Toney]

Sorry, I never used Gowin.
The limitation is usually set by the compiler & trying to trick the Compiler/FPGA can lead to PLL instability.

Installing the software. Unfortunately, I have not seen anything in the documentation yet on how to use the software, let alone set the PLL. But, according to the documents the oscillator can be set to frequency of 100MHz (or at least 50MHz), also enough to double the clock with acceptable jitter. If the PLL worked out of spec, that would be fantastic though.

The documentation I am reading is for the GWIN-1, I wonder what the "LV" stands for in GW1N-1-LV.

[langwadt]

Sorry, I never used Gowin.
The limitation is usually set by the compiler & trying to trick the Compiler/FPGA can lead to PLL instability.

Installing the software. Unfortunately, I have not seen anything in the documentation yet on how to use the software, let alone set the PLL. But, according to the documents the oscillator can be set to frequency of 100MHz (or at least 50MHz), also enough to double the clock with acceptable jitter. If the PLL worked out of spec, that would be fantastic though.

The documentation I am reading is for the GWIN-1, I wonder what the "LV" stands for in GW1N-1-LV.

I'd guess Low Voltage, 1.2V core voltage

this might help, https://www.gowinsemi.com/upload/database_doc/39/document/5bfcff2ce0b72.pdf

[asmi]

This thread is a good example of how NOT to go about FPGA project. What you should do is determine approximately how much of FPGA resources (LUTs, FFs, memory, DSP, etc.) your design will need, and only then proceed with selecting device and a board, instead of picking up a random board and trying to cram you design into it somehow. You've got to remember that FPGA and devboard is just a tool, so you pick the right tool for the job, and not take out a random tool and then try to use it for everything you can think of.

[Foxxz]

This thread is a good example of how NOT to go about FPGA project. What you should do is determine approximately how much of FPGA resources (LUTs, FFs, memory, DSP, etc.) your design will need, and only then proceed with selecting device and a board, instead of picking up a random board and trying to cram you design into it somehow. You've got to remember that FPGA and devboard is just a tool, so you pick the right tool for the job, and not take out a random tool and then try to use it for everything you can think of.

He could have probably done it with a raspberry pi zero and a few command line programs strung together but where is the learning experience in that? 

[Toney]

This thread is a good example of how NOT to go about FPGA project. What you should do is determine approximately how much of FPGA resources (LUTs, FFs, memory, DSP, etc.) your design will need, and only then proceed with selecting device and a board, instead of picking up a random board and trying to cram you design into it somehow. You've got to remember that FPGA and devboard is just a tool, so you pick the right tool for the job, and not take out a random tool and then try to use it for everything you can think of.

I see your point. However, I am quite the noob and it's unlikely that I get all the details down even if I wanted. Nonetheless, here is the summary:
- PLL (2.82MHz -> x4)
- External power
- Enough resources to run the code above. The report below.

HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 8x6-bit ROM                                           : 1
# Adders/Subtractors                                   : 10
 1-bit adder                                           : 5
 10-bit adder                                          : 1
 3-bit adder                                           : 1
 5-bit adder                                           : 1
 6-bit adder                                           : 2
# Counters                                             : 3
 3-bit up counter                                      : 1
 6-bit up counter                                      : 2
# Registers                                            : 143
 1-bit register                                        : 12
 10-bit register                                       : 1
 2-bit register                                        : 128
 5-bit register                                        : 1
 6-bit register                                        : 1
# Comparators                                          : 2
 5-bit comparator greatequal                           : 1
 5-bit comparator less                                 : 1

Rasberry pi zero is an interesting option, too. I am not sure it's able to read four 88.2kHz streams and maintain the required precision though. I did look at some MCUs and that was the problem. FPGA seems to lend itself to the task more naturally.

[BrianHG]

If the gowin PLL wont cleanly lock onto your '2.82MHz' clock, just use 2 inputs programmed into a combinational XOR gate with an output feeding back into the gowin's CLK input.  All you need is the right inductor/cap/resistor between the 2 inputs & you will have a 5.64MHz clock which it can safely lock onto.  If you need tuning, the cap can be a varicap.  You tune with a scope on the output looking for an approximate 50/50 duty cycle.

There are other ways to do this as on another FPGA thread on this board, I've successfully made a an Intel FPGA's PLL lock onto a 15.7KHz source clock with a 42MHz output with a jitter less than ~ +/-250ps using 2 PLLs in the FPGA, if I recall.

[langwadt]

If the gowin PLL wont cleanly lock onto your '2.82MHz' clock, just use 2 inputs programmed into a combinational XOR gate with an output feeding back into the gowin's CLK input.  All you need is the right inductor/cap/resistor between the 2 inputs & you will have a 5.64MHz clock which it can safely lock onto.  If you need tuning, the cap can be a varicap.  You tune with a scope on the output looking for an approximate 50/50 duty cycle.

the pll might not like the jitter from using both edges, though the data sheet doesn't seem to mention it

[BrianHG]

If the gowin PLL wont cleanly lock onto your '2.82MHz' clock, just use 2 inputs programmed into a combinational XOR gate with an output feeding back into the gowin's CLK input.  All you need is the right inductor/cap/resistor between the 2 inputs & you will have a 5.64MHz clock which it can safely lock onto.  If you need tuning, the cap can be a varicap.  You tune with a scope on the output looking for an approximate 50/50 duty cycle.

the pll might not like the jitter from using both edges, though the data sheet doesn't seem to mention it

I know in the Intel FPGAs, you can program the PLL loop filter bandwidth down to ~500KHz which you smear that out.
Noise shouldn't be too bad as the jitter will only be really amplified if the source clock has jitter on one edge.

[Toney]

I have been waiting for the license for the software, I believe they email it. I did not see any information on how to call the PLL in the documentation, but perhaps it is self-evident once the software becomes functional.

[langwadt]

I have been waiting for the license for the software, I believe they email it. I did not see any information on how to call the PLL in the documentation, but perhaps it is self-evident once the software becomes functional.

You can download the license file from SiPeed website and you need to change your MAC address to spoof the license manager to think your computer is the originally licensed computer.

lol, that doesn't sound sketchy at all

[asmi]

lol, that doesn't sound sketchy at all

Yea, I thought that too
But even if you ignore that, there remains a practical question of what do you if you have other software that is tied to your current MAC address. Quite a bit of commercial software does that.

[langwadt]

lol, that doesn't sound sketchy at all

Yea, I thought that too
But even if you ignore that, there remains a practical question of what do you if you have other software that is tied to your current MAC address. Quite a bit of commercial software does that.

can't have multiple interfaces (possibly virtual) with the needed mac addresses ?

[asmi]

can't have multiple interfaces (possibly virtual) with the needed mac addresses ?

Nope, I don't get to control which interface licensing software uses. It always picks physical interface at least on my PC, even though I've got few virtual NICs as well.