Advice for Altera Beginner

[fchk]

Hi();

I've got some experience with Xilinx and Lattice, but no project with Intel/Altera. I will use a Cyclone 10 GX, the smallest one 10CX085 in 484UBGA.
Application is some kind of Time-of-Flight measurement, so my manager opted for a 20nm part in order to have fast logic blocks.

I will do all of hardware, VHDL and firmware.

After reading dokumentation there are some questions left:

1. Configuration Flash:
I'm going to use Active Serial configuration with an ECPS-L 256. CS, CLK and data pins are dedicated pins on the package. Is it possible to access the flash after loading the FPGA.
I will have some kind of interface to a microcontroller, most likely SPI. How can I upgrade the ECPS flash from the microcontroller or use part of the flash for other purposes?

2. Power and Bypass Caps:
Xilinx has got a nice list which and how many bypass caps are required on which power rail. My understanding of the Intel/Altera way is that I'm supposed to use a power estimator in order to get estimates for power requirements and bypass caps. The problem is that I'm in a too early state and just don't have any numbers to fill in for my first test board. For this reason I need a worst-case starting point from which I can then scale down for the final product. Where can I find maximum power reqirements for all the rails and worst case bypass cap requirements?

3. HSSI Transceiver part:
I won't need the high speed transceiver parts yet. They have extra 0.95...1.03V power rails. What power requirements do theses rails have? Can I cut corners and simply use the 0.9V core voltage if I don't use the transceivers anyway?

Thanks for help.

[ejeffrey]

Note that I have only used the V series FPGAs (mostly the Arria V).  I think the 10 series is the same, but there might be differences.

Yes you can access the configuration flash after the FPGA loads.  Altera provides some flash IP to help with that.  If you just want to use the left over flash to store data then you are pretty much done.  I haven't actually used this, but as I understand it their provided serial flash IP also understands the bitstream table of contents format.  You can do is create a multi-page .POF file where the first page is the FPGA bitstream and one or more subsequent pages are data blocks.  That way you automatically access the correct flash offset even when your FPGA bitstream changes size.

If you want to use the extra memory to support field upgrading or alternate bitstreams then you are expected to use the partial reconfiguration support.  In this case, there is a bare-bones FPGA base image that acts similar to a bootloader plus one or more application images.  The base image starts up and then selects which image to use and triggers partial reconfiguration.  The idea is that you can have a "factory" application image plus a user updateable image.  The "bootloader" will try to load the user image.  If that fails for some reason it falls back to the factory image.  This protects you against failed upgrades.

By default once configuration finishes the SPI pins go high impedance.  It is possible (and I have done this) to connect a microcontroller SPI master in parallel to the FPGA.  As long as you are careful about sequencing the microcontroller can do flash updates.  For this you will want the microcontroller to also be connected to the nCONF, nSTATUS, and CONF_DONE pins of the FPGA so that it can control the configuration sequence and knows when it is complete or has failed.

A more complicated but more flexible way to do this (and one that is common on dev boards) is to switch from active serial mode.  For  instance a lot of dev boards use a MAX V or MAX10 CPLD that reads data from the SPI flash and programs the FPGA via the passive serial or passive parallel interface.  Now you can connect a microcontroller to the CPLD to read/write the flash chip.  Alternately you could just use a microcontroller instead of a CPLD which will be easier to program but may not boot as fast.

Note that this is all for FPGAs without hard processors.  SoC type FPGAs can configure via active serial but normally do not.  Instead, the HPS boots first and then loads the FPGA bitstream.  This allows the bitstream to be stored anywhere the HPS can access -- it can be SD or eMMC flash, over a network or USB connection, or anything else.