I've been looking at websites describing different methods for dividing a clock signal using DFlip-Flops and a few gates and I can simply copy the circuits, simulate them and it works.

What is often missing in tutorials and videos is what methods can be used to create these circuits yourself.

I'm assuming you want to learn how to deisign clock dividers directly from logic gates.

(Otherwise yes, using a HDL you can use counters, which are easy to describe, and either comparators if the dividing factor is not a power of two, or just directly use the corresponding bit of the counter if the dividing factor is a power of two. Done.)

For that, what you basically need to learn is how to design counters from flip-flops. It's really basic knowledge and you'll find this pretty easily. Then you will possibly need to learn how to design comparators (again if the factor is not a power of two, otherwise that's useless.) If you don't know where to start, I'm sure Wikipedia has articles for both, although getting yourself a good book about digital logic would be a good idea.

As a side note, if you're considering implementations on FPGAs - whatever approach you use, schematics or HDL - you need to be careful with such hand-implemented dividers. In most cases, their output can't properly drive internal clock distribution trees, so the timing results will be pretty poor. This has been discussed several times in other threads, so I suggest searching the forum for this particular topic if you're interested.