I'm afraid you can't use that board to drive LVDS because 7 series FPGA's IO bank needs to be powered by 2.5 V in order to output LVDS (inputs are possible with any Vccio if you don't use on-chip termination and instead use external resistors), and as far as I remember Cmod A7 is a 3.3V-only system. Answering questions 2 and 3 seems pointless in light of that, but in general all differential pairs of 7 series FPGAs are identical and can reach the same data rate using SERDES (950 Mbps for speed grade 1, 1250 Mbps for SG 2 and 3). As for SI, I think your main issue will be a lack of length matching (both within diff pair and between lanes) and not necessarily connector itself.