Combinatorial inside or outside of a process

[emece67]

.

[SiliconWizard]

Actually, the subset of VHDL that is potentially synthesizable is not that small IMO (but let's not nitpick about what small means - I'm just saying this because I have seen many people shy away from some useful language features that are perfectly fine for synthesis in the general case.) Main problem is, as you said, that most vendors tend to use slightly different subsets depending on the underlying hardware (which is understandable but could make things hard for designers.)

So yes, read the docs for your synthesis tools.

This "process" thing, with their sensitivity lists, I think, was interesting, because it's one of the VHDL features that is not necessarily intuitively non-synthesizable. So that was interesting IMO as a reminder.

The small "exercise" I showed about how to possibly implement them in hardware was also interesting (at least to me!), and was an attempt to show why that would be hard to synthesize (to the point of not making much sense). I'd be curious what others could come up with, if anyone feels like trying.

[emece67]

.

[SiliconWizard]

Yep, nice find. (You cheated a bit by letting the synthesizer figure out some hardware implementation for you, but at least you know it's synthesizable.)

In my approach, I didn't think of optimizing for the specific logic operation (AND), and provided a solution for C being any combination of A and B, so I think my solution was more general. Optimizing is of course clever, but it shows that the problem can't be solved with such simple hardware in the general case.

Whereas your goal was likely to eventually provide the hardware structure, I'll give a bit of caution though, related to synthesis for FPGAs specifically: using asynchronous signals to "clock" some process (so eventually as a clock for FF's) is in general a bad idea. The internals of FPGAs, notably FF's, are optimized for clocks with some minimal characteristics (skew for instance). So, using this kind of process is likely to give all kinds of issues if 'a' is a random asynchronous signal, and usually timing analysis will also not be conducted properly, leaving you in the unknown. Another issue is that if 'a' and 'b' are not on the same clock domain, the you're going to have metastability issues. So I certainly don't suggest doing this on FPGAs.

[emece67]

.

[emece67]

.

[SiliconWizard]

Certainly. I think the warnings we express are worthwhile though for people not aware of the pitfalls and tempted to do this kind of stuff.

As to the challenge, my point, beyond a fun challenge thing, was to illustrate why sensitivity lists were usually ignored by synthesis tools.