Author Topic: Complete newbie looking for a good practical beginers guide to programming FPGAs  (Read 2173 times)

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Offline Garry G

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Hello, so I recently bought a cheep Altera Intel FPGA Development Board  to just play around with and hopefully learn to do something simple with. The board I have is a QMTEK Cyclone IV SDRAM Starter Kit (Model: EP4CE15F23).
Now I assume this if fairly rubbish, as it was fairly cheep, but as I said I just want something to learn the basics on. I've been a professional programmer for many years, but only ever an armature with electronics. I would say I only know the basics, although I am familiar with Boolean algebra type logic and assembly level programming. So I didn't think I'd be starting completely from nothing!

However, I'm finding this very confusing so far. Probably because my cheep board came with no instructions, unless you count a bit of paper with Chinese on it! I have googled and found many things, most of which appear to contradict each other.
I downloaded the Quartus II (free) version 13 software with what I believe to be the correct driver for my board, but this is a bit bewildering when you have no idea where to start.

I was hoping someone could point me in the direction of some good beginners resources. I'm sure there must be good beginner books written about starting out with FPGAs.


If I can get to grips with this it could be useful in my day job.



Thanks,


 

Offline dorkshoei

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I was in the same boat as you.  I bought the open source Ice Breaker. 

https://github.com/icebreaker-fpga/icebreaker
 

Offline NorthGuy

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Programming FPGAs has nothing to do with programming CPUs. You don't write instructions which execute in run-time as you would in assembler or in C. Rather you design the hardware, then you describe it. The tools then implement it and configure FPGA accordingly. You also can write test-benches which simulate your code to make sure the hardware you described works as you expected.

There are two routes you can go.

If you want to learn low level things, figure out what are registers (flip-flops) and what is combinatorial logic (LUTs), and how they combine together to produce RTL designs.

If you want to learn from the top, find the IPs you need (IP stands for "Intellectual Property" but in reality these are pre-designed blocks of logic), figure out how to connect them and go from there.

I'm sure there will be posts which recommend languages to start with, but it doesn't really matter - all of them can describe the hardware and do so very similarly. Select the language which is supported by your tools. If you like C, select Verilog or better yet SV. If you like Pascal, select VHDL.
 
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Offline voltsandjolts

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I have the same QMTECH board and I think its good value. Not ideal for SoC/softcore stuff but for learning HDL it should be fine.

You can download the schematics, manual and demo verilog projects here.
You will need a USB Blaster download cable (about £8 on ebay for the knock-offs that I use).
Latest signed driver attached, as you normally have to download Quartus 21 to get it (6GB download).

I've also attached the TCL pinout file I use for this QMTECH board.
After you have created a new project go to Tools > Tcl scripts, select and run it.
All the IO pins used by board hardware are then named as shown in Assignments > Pin Planner.

You can use the latest Quartus if you like, although I use 20.1 which comes with ModelSim rather (newer Quartus uses Questa for sim).

Good luck and have fun.
« Last Edit: November 28, 2021, 04:11:13 pm by voltsandjolts »
 

Offline dorkshoei

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There are also several online classes on udemy but they usually (obviously) target a specific board.
 

Offline bingo600

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Offline rstofer

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If you want to mess with CPUs, I'm going to mention LC3 as a worthy project used by many universities as part of their curriculum.  I'll do one better and give you an implementation along with links to the documentation which is all over the Internet.  Just Google for 'LC3' or 'LC3 Appendix'.

https://www.eevblog.com/forum/fpga/alu-in-mips/msg3698950/#msg3698950

I don't know that this will fit in the board you bought, I only ever stuffed it in a Digilent Nexys 4

https://digilent.com/shop/nexys-4-artix-7-fpga-trainer-board/

I haven't used it for much but the included code consists of interrupt driven console input over a USB-> Serial port that is implemented on the board as part of the boot loader.  PuTTY is helpful:

https://www.putty.org/

You might get some ideas about coding - for better or worse.  It isn't necessary to actually build the project.  Look at the big 'case' statement starting at line 437 in LC3.vhd to understand how the instructions are actually implemented.  You will see how the 'case' statement follows the transition diagram in the documentation.

Take the logic block diagram in one hand and the code in the other and see how they match up.  See how all the MUXs are laid out exactly from the diagram.  There's a chunk of VHDL for every block in the diagram.  I suppose I should have labeled them but I didn't.  Pay attention to the parallel banks of registers.  This structure isn't defined in the documentation but it allows for instruction that read two operands and store a result to use the same register both sources and the destination.  Both banks are written at the same time.  An instruction like:

Add R0, R0, R0 - which would add R0 to itself (doubling the value) and storing the result back in R0 all in one cycle.

Have fun!

 

Offline james_s

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Free Range VHDL that somebody linked above is what I found most useful. There is a very steep learning curve with FPGAs but once you get the hang of it they are incredibly cool. Previous programming knowledge is arguably more hindrance than help because as was already pointed out HDL only looks like a programming language, in reality it is a completely different paradigm, you are not writing instructions that are executed, you are describing a digital circuit. If you fall into the trap of trying to write it like a program that will cause you all sorts of problems.

Far from "fairly rubbish" the EP4CE15F23 is about 3 times the size of the FPGA I have used in most of my projects and I've implemented entire 8 bit computers and early arcade games. It will probably be several years before you are approaching the limits of that FPGA depending on what you are trying to do. A larger FPGA has disadvantages, it takes much longer to do the equivalent of compiling.
 
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Offline rstofer

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Programming FPGAs has nothing to do with programming CPUs. You don't write instructions which execute in run-time as you would in assembler or in C. Rather you design the hardware, then you describe it. The tools then implement it and configure FPGA accordingly. You also can write test-benches which simulate your code to make sure the hardware you described works as you expected.

There are two routes you can go.

If you want to learn low level things, figure out what are registers (flip-flops) and what is combinatorial logic (LUTs), and how they combine together to produce RTL designs.

Exactly right!  There are only a few constructs that need to be understood.  Everything else is just wiring them together.  Registers, counters, FFs, encoders, decoders, MUXs, BlockRAM, external RAM (I prefer static RAM for obvious reasons), logic statements and others I'm overlooking.  Regardless of what you ultimately build, these fundamental blocks will be used.

There are multiple ways of implementing finite state machines.  I use the two process approach while others prefer one process and still others like the three process approach.

The "Free Range VHDL" book linked above is quite good.   VHDLwhiz.com is also very good but he has changed to a subscription model so I don't know how much of his stuff is still free.  He tends to spend a lot of time on simulation with ModelSim.
 
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Offline mon2

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Recommend to learn Verilog and highly highly suggest to review the great Jean's website:

www.fpga4fun.com

Every page of this website is a gold mine to learn from.
 

Offline voltsandjolts

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If you like C, select Verilog

I would say, if you like C, select VHDL, because you'll be less confused :P
 
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Offline Garry G

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Thanks for all the resources you've given. This should keep me busy for a while.

I still (have to) program in C# as part of the day job, so if they use a similar syntax I suppose that Verilog or SV may be best for me. Although I have used Pascal/Delphi in the past.
I do already have a USB Blaster cable, so hardware wise it looks like I'm good to go.
It's good to know that I've actually got something decent for the money.


I just have a few questions:

Someone said to download Quartus II v13 for the board I have, don't know why. So is a later version of Quartus still compatible with my board then?

I understood the circuit building process to be similar to Boolean Algebra in that you are describing the actual components and their connections (and, nand, or, nor... etc) logic through the various 'languages' used, in order to create a circuit on the FPGA chip using software-defined components.
Is this a correct analogy?

Are all IPs basically Logic Blocks, or are some representations of entire boards/machines?
Do you have to pay for all of these if they are intellectual property?


 

Offline fourfathom

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I still (have to) program in C# as part of the day job, so if they use a similar syntax I suppose that Verilog or SV may be best for me. Although I have used Pascal/Delphi in the past.

I understood the circuit building process to be similar to Boolean Algebra in that you are describing the actual components and their connections (and, nand, or, nor... etc) logic through the various 'languages' used, in order to create a circuit on the FPGA chip using software-defined components.
Is this a correct analogy?

Are all IPs basically Logic Blocks, or are some representations of entire boards/machines?
Do you have to pay for all of these if they are intellectual property?

The C / C# / Pascal comparisons aren't really that useful.  There are some syntax similarities, but many differences and, more importantly, the way you use Verilog or VHDL to define hardware is quite different than how you structure programs.  I use Verilog, but no doubt VHDL is just as good.

The first step is to get your tools and process working with the simplest "Hello World" design possible: blink an LED attached (through a series resistor) to an FPGA output pin.  Once you can make that work then it's time to start designing more complicated stuff.

You can design by connecting nand, nor, etc, components, but for anything at all complicated you will be using higher-level constructs, with some interspersed Boolean logic.  The HDL converts these to gates and other FPGA primitives.

The IP logic blocks may be free, or there may be licensing required.  The FPGA I am currently using (Lattice MACHX02) includes logic blocks such as RAM, FIFO, PLL, I2C, SPI, and others.  These use a combination of hard-wired internal elements and HDL.  Most of these are free, but I think some require payment.  I wouldn't worry about the IP blocks until you are comfortable with basic HDL design.

 
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Offline james_s

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Various versions of Quartus II support various families of chips, I am not up to date on what supports what but I use 13.0sp1 which supports the Cyclone II parts I'm mostly using. You can have multiple versions installed though and they coexist just fine, the only issue is the multiple gigabytes each consumes but space is cheap.

I would suggest trying Verilog and VHDL and seeing which one makes the most sense to you. Personally I prefer VHDL and far more of the hobbyist FPGA stuff out there uses it but both languages have identical capabilities, anything you can describe with one you can describe with the other and you can even mix and match using both in the same project.

There are varying abstraction layers which you can use to describe circuits ranging from gate level where you describe the individual gates up to a much higher level behavioral modeling where you describe the behavior of complex circuits and you can use various combinations of these together.

The equivalent to the classic "hello world" program is probably going to be a counter driven by a clock with one of the lower bits driving an LED.
 

Offline rstofer

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Earlier I posted a link to a message where I linked a sizeable bunch of VHDL.  It isn't a book exercise, it really implements a CPU.  Not a great CPU but one that is workable for some definition of work.

Read through the code and see if it is understandable.  I think it is quite easy to read the code and envision the matching hardware or, more importantly, envision the hardware and describe it in code.  Spread the two appendices out on a table and wander through the code, side by side.  See how it matches, thought for thought.  At least that's the way I see it.

I do not get the same fuzzy feeling with Verilog or at least the Verilog I have seen.  System Verilog is starting to look a lot like VHDL and may be more the kind of language I could understand.  But I see no reason to change.

I probably use VHDL because my first 'blinking LED' was written in VHDL.  Had I started with Verilog, I would probably still be using it.

It is possible to make small demo projects in all 3 languages and see the difference but when you are talking about multiple thousands of lines of code, the idea of converting between languages just takes too much effort.
 

Offline colorado.rob

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Hello, so I recently bought a cheep Altera Intel FPGA Development Board  to just play around with and hopefully learn to do something simple with. The board I have is a QMTEK Cyclone IV SDRAM Starter Kit (Model: EP4CE15F23).
Now I assume this if fairly rubbish, as it was fairly cheep, but as I said I just want something to learn the basics on. I've been a professional programmer for many years, but only ever an armature with electronics. I would say I only know the basics, although I am familiar with Boolean algebra type logic and assembly level programming. So I didn't think I'd be starting completely from nothing!

However, I'm finding this very confusing so far. Probably because my cheep board came with no instructions, unless you count a bit of paper with Chinese on it! I have googled and found many things, most of which appear to contradict each other.
I downloaded the Quartus II (free) version 13 software with what I believe to be the correct driver for my board, but this is a bit bewildering when you have no idea where to start.

I was hoping someone could point me in the direction of some good beginners resources. I'm sure there must be good beginner books written about starting out with FPGAs.

I can recommend this very extensive video series from LBE Books:



It will cover the basics that you would expect in a college course on FPGA design.  The only thing I did not like is that the video lessons are in VHDL and I prefer Verilog.  The video series follows along a pair of FPGA design books, one in Verilog and one in VHDL, covering the same material.  (This is the book I purchased: https://www.amazon.com/Digital-Design-Using-Digilent-Boards/dp/0982497091.)  The video series is a very well structured introduction to FPGA development.  I probably gained more from the series doing the lessons in Verilog if only because I had to think about the problems outlined in the videos more conceptually.  You will need to translate the exercises into whatever hardware you are using.  Most problems do not require a specific board.  I did all of the exercises using the programmable logic (PL) resources of a Pynq Z2 board, along with some PMODs and add-on boards.

I, too, come from a software background so we both understand that, whether programming or HDL, language is just a matter of preference.

I should also say that I am really fond of the Pynq development environment, which links ARM Linux systems with the FPGA resources of the Zynq platform via Python.  It is great for prototyping HDL designs.  And HLS, high-level synthesis, using C++, is an amazing productivity booster once you get the basics of digital design down.  These days almost all my designs use some combination of HDL, HLS, and IP Integrator blocks, and are almost always prototyped using Pynq.

Just know that everything I do is hobby-level stuff.
 

Offline asmi

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When you design for FPGA, you've got to think in terms of designing a digital circuit, not executable code, because there is nothing in FPGA that can actually execute that code (unless you put some soft of CPU there yourself, that is). With that in mind, similarities of HDLs to "normal" programming languages is deceptive and can lead to serious issues with the design.

So before you do anything, you need to understand what FPGA is (a sea of LUTs and flip-flops with some other hardware blocks sprinkled in - like block RAM, or DSP blocks, PCI Express, multi-gigabit transceivers, etc.). Here is a playlist with the best video tutorials I've ever came across: https://www.youtube.com/playlist?list=PLnAoag7Ew-vr1M98Q5K2kLHxFQ5l0DU3B

He uses different FPGA board in there, but the content for the most part is equally applicable to any more-or-less modern FPGA devices. He also does all lessons in both VHDL and Verilog, so you can readily compare and contrast them.

Offline rstofer

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I understood the circuit building process to be similar to Boolean Algebra in that you are describing the actual components and their connections (and, nand, or, nor... etc) logic through the various 'languages' used, in order to create a circuit on the FPGA chip using software-defined components.
Is this a correct analogy?

Combinatorial logic like NAND, NOR and NOT don't necessarily form interesting projects.  You need some idea of sequential circuits and 'state'.  Do this, do that and finally, do this other thing on various clock edges.

You will almost never concern yourself with gate level logic, the tools work at that level.  You declare a register as a logic vector of some width and a related process to make it register some value on some clock edge.  You do not concern yourself with the D-flops that implement the register.  The only difference between a register and a counter is in the process that drives it.  You define a MUX in terms of its input and output characteristics, you would almost never actually implement the MUX in gate level logic.  You could but you just wouldn't.  It's the tool's job to work at the bottom level.  I have never used a Karnaugh map for FPGA projects.  The tool does that kind of thing.

Again, read through that LC3.zip file, especially LC3.vhdl, and see what you think.
« Last Edit: November 29, 2021, 12:42:34 am by rstofer »
 

Online BrianHG

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You will almost never concern yourself with gate level logic, the tools work at that level.  You declare a register as a logic vector of some width and a related process to make it register some value on some clock edge.  You do not concern yourself with the D-flops that implement the register.  The only difference between a register and a counter is in the process that drives it.  You define a MUX in terms of its input and output characteristics, you would almost never actually implement the MUX in gate level logic.  You could but you just wouldn't.  It's the tool's job to work at the bottom level.  I have never used a Karnaugh map for FPGA projects.  The tool does that kind of thing.

You still need to understand the fundamentals going in.  Understanding how to efficiently derive logic and how it usually impacts FPGA performance at the higher end when you design code to either run really fast or occupy minimal space.  You do not want to fall into a trap where you may see no other choice but to redo everything where there are sometimes a simple solution.

My first issue with most of the online lessons is that they don't come to the simple grip of what the compiler is doing in the FPGA depending on how you choose to code.  Taking the route of 'I don't care and just let the compiler sort it out' can lead to designs which can never achieve a high FMAX, designs with sloppy or noise output timings, or even designs which can have meta-stability issues.

I provided here 3 examples of the same source code with pictorial and described how the compiler implements the results in the FPGA with the pros & cons:  https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg2767312/#msg2767312

Surprisingly, even a seasoned Verilog coder friend of min a number of years before this post didn't grasp how this coding changed the compiler's choice of implementation and consequences in the greater design within the FPGA.

Understanding what the compiler tries to do with your code helps you construct a better design.
« Last Edit: November 29, 2021, 01:25:48 am by BrianHG »
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Online BrianHG

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One last recommendation I can make: I know it adds complexity and delay in learning an HDL language -> to -> functioning hardware to play with, but don't make the mistake I did at the beginning.  Make an effort early on to learn how to use one of the industry standard HDL simulators natively on it's own.  Not just compiling and running the simulation through Quartus.  When installing Quartus, you get Modelsim which is available and also functions with Lattice and Xilinx's development tools.  Learn how to compile and simulate portions of your work running Modelsim on it's own outside Quartus.  Once you have a working design, then bring in that code to Quartus to drive your FPGA.  As your design sophistication increases, the faster it is to develop and debug all within Modelsim and it's 1 second compile time instead of waiting for Quartus to build an entire FPGA.
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Offline rstofer

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The tools will often tell you which path(s) are constraining speed.  The problem with Vivado is that it won't directly list a maximum clock rate.  What it does is let the user do the calculation:

https://support.xilinx.com/s/article/57304?language=en_US
 
There are clearly constructs that are time sinks like if - else if - else if - else if - else endif which generates a priority tree.  Others are more subtle but the synthesizer will usually show the worst case paths through the logic.

Some tools (like ISE or Vivado) will display the RTL Schematic which is a diagram of the logic that was actually generated.  It should have been obvious that a Register <= Register + 1; would drag along an N bit adder.  I don't know what I expected but that wasn't it!

At 100 MHz, almost any logic will run in an Artix 7.  Getting to 200 MHz and beyond is going to take talent.  And pipelining...  But that is a topic for much later.  In the 'blinking LED' stage, not much of this stuff really matters.

 

Offline fourfathom

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Since the OP mentioned programming in c#, one similarity with HDL design is that c# and many other modern programming languages support event-driven programming.  In that case you have routines that don't execute as part of the top-level program flow, but instead execute when triggered by a timer, an interrupt, or some other event, and then communicate somehow to the main program.  HDL is much like this, in that the resulting logic is triggered by various clocks and enables.  With a HDL design (or any hardware design) it may actually be easier to coordinate these various event-driven elements, than it is with a software program.

Anyway, it might be a helpful way to look at HDL design in general.
 

Offline james_s

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Some tools (like ISE or Vivado) will display the RTL Schematic which is a diagram of the logic that was actually generated.  It should have been obvious that a Register <= Register + 1; would drag along an N bit adder.  I don't know what I expected but that wasn't it!

Quartus does too, it's called RTL Viewer.
 
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Offline bingo600

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Some tools (like ISE or Vivado) will display the RTL Schematic which is a diagram of the logic that was actually generated.  It should have been obvious that a Register <= Register + 1; would drag along an N bit adder.  I don't know what I expected but that wasn't it!

Quartus does too, it's called RTL Viewer.

As a beginner ...
IMHO Quartus RTL Viewer is much better that ISE's.
But i guess it might depend on, what you are used to.

I just think the Quartus RTS is presented much nicer.

Re Constraints ... I wish there was some quick intro into the "timing setup" for ISE/Quartus.
That is "black magic" for a beginner.

I'm mostly using Quartus , because i use the Cheap EPM-240 CPLD boards from Ali.
And the Cheap CycloneII boards, for the Grant "Multicomp" i have running MC6809 & FLEX  (Trip down memory lane... My first PC was such a beast)

Who just decided to stock up, before they "dry out"
5 x EPM-240 CPLD  (Blue , Red has lousy decoupling)   = $40
https://www.aliexpress.com/item/33007628845.html

2 x Altera Cyclone IV FPGA = $50
https://www.aliexpress.com/item/1005002121650778.html

2 x Xilinx Spartan6 w SDRam = $48
https://www.aliexpress.com/item/1005001502949190.html

All prices including 25% VAT + Ali shipping

I got them all , and now they seem to have dried out , at least from where i bought.


I have no idea what to use the FPGA boards for right now
I struggle with VHDL .. But just lack of experience.
And The challenge that  i'm used to "C" & sequential flow  :scared:

Someone described that situation excellent above.

Right now i'm using Quartus 13-sp1 , and ISE 14.7.
Installed in a Linux Mint 17.3 VirtualBox.
I can't get the "El-cheapo" USB Blaster to work on Vbox USB -  works in Native linux.
I mean The little black/blue - https://www.aliexpress.com/item/1005001406394705.html

But i have another USB Blaster , made/cloned from the real Altera with FTDI + CPLD .. That one works.
And the Xilinx Clone also works n Vbox USB.


/Bingo


 

Online emece67

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One last recommendation I can make: I know it adds complexity and delay in learning an HDL language -> to -> functioning hardware to play with, but don't make the mistake I did at the beginning.  Make an effort early on to learn how to use one of the industry standard HDL simulators natively on it's own.  Not just compiling and running the simulation through Quartus.  When installing Quartus, you get Modelsim which is available and also functions with Lattice and Xilinx's development tools.  Learn how to compile and simulate portions of your work running Modelsim on it's own outside Quartus.  Once you have a working design, then bring in that code to Quartus to drive your FPGA.  As your design sophistication increases, the faster it is to develop and debug all within Modelsim and it's 1 second compile time instead of waiting for Quartus to build an entire FPGA.


This!

What I'll say now is debatable, but my advice is to conceive the simulator as the "central" tool where you'll do much of the work. Use Quartus/ISE/Vivado/whatever_other_vendor_tool to compile the design into a bitstream only when you know it will work because the simulations say it will work. Quartus/ISE/Vivado may then say to you that the design does not achieve the time/area/power specs, then re-design whatever is needed to achieve the specs, but again using simulations to validate your changes. Do not use the board during development/debugging, but the simulator.

When using IPs, use the vendor tool to generate simulable models for them and in order to be incorporated into the simulations.

And yes, better use a stand-alone, capable simulator (the ModelSim included with Quartus can be used with absolute independence from Quartus itself).

In case you are still in the VHDL vs. (System)Verilog dilemma, although I really better like VHDL, I think that SystemVerilog (not bare Verilog) is the most future-proof HDL now.

Regards.

Information must flow.
 


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