Converting a two level analog signal to two bits digital in Cyclone IV or/and V

[BrianHG]

OMG, an 8$ chip when a (looking at your first scope shot) 0.50$ 74ALVC04 powered with 2v (yes, this ICs inputs are 3.6v tolerant even powered with 2v) and 2 diodes will do the same job, though the logic switch edge will be fixed at ~1v on each input.  Powering your IO bank at 3.3v would mean no ICs needed, just the 1-2 silicon diodes to separate the 2 voltage levels to 2 different inputs.

Ok, back to your question:
For CycloneIV, you have 0.3-0.5v above the VCCIO before the clamping diodes engage.
An output resistor divider would work with your illustrated circuit.
A 1k series resistor alone would also work so long as the selected IO pin has the PCI clamp diodes mentioned in the CycloneIV hand book in section 3, DC electrical characteristics.

As for powering an IO bank with 3.3v and telling quartus to run the IOs in differential 2.5vLVDS, I don't think it will destroy the chip, however, I never done this.

Can you change your dev board's 3.3v regulator to 2.5v?
Most other 3.3v lvcmos ICs should work at 2.5v, but a bit slower.

[langwadt]

I think the title of my post should have been "How did that guy do it?". Considering that he fed the signal to two inputs directly through two zero ohm resistors, I suspect he used differential inputs with the negative side to two different levels, I don't know what's on the bottom side of the board, but I suspect there are two voltage dividers.

Assuming it's done exclusively with divider resistors, I would not personally guarantee such a design over many FPGA & pcbs.

why not? looking at the spec for LVDS inputs: Vcom = 0.05-1.8V, Vdif = 100mV

so divide input by 2 to get inside the common mode range, and two dividers to set the thresholds

This is what I'm talking about. It seems to work very well in simulation.
Since my development board has all VCCIOs connected to 3.3V, I wonder what happens if I assign 2.5V LVDS pairs but the bank is supplied by 3.3V. Is it going to blow up the chip, or is just the levels are messed up? I'm aware that all the I/Os in that bank must be 2.5V, otherwise Quartus will swear at me...
Rename .txt to .asc to simulate in Ltspice.

Don't know about Intel but Xilinx has said that LVDS inputs will work just fine at 3.3V but the if you use the internal termination it not be accurate

Outputs won't work in the newer families because the faster LVDS transistors are disconnected about ~2.9V to protect them

[Miti]

OMG, an 8$ chip when a (looking at your first scope shot) 0.50$ 74ALVC04 powered with 2v (yes, this ICs inputs are 3.6v tolerant even powered with 2v) and 2 diodes will do the same job, though the logic switch edge will be fixed at ~1v on each input.  Powering your IO bank at 3.3v would mean no ICs needed, just the 1-2 silicon diodes to separate the 2 voltage levels to 2 different inputs.

Brian, the comparators are not extra chips. They're supposed to be the internal FPGA LVDS comparators. I used those chips only for simulation and I selected the resistors to bring the common mode inside the 0.5 to 1.8V range.

As for powering an IO bank with 3.3v and telling quartus to run the IOs in differential 2.5vLVDS, I don't think it will destroy the chip, however, I never done this.

Can you change your dev board's 3.3v regulator to 2.5v?
Most other 3.3v lvcmos ICs should work at 2.5v, but a bit slower.

I think I could do that. Actually there is a 2.5V regulator on the board, I could just remove the 3.3V and connect 2.5V and 3.3V line. I don't think the VCCIOs need too much current.

[Miti]

Don't know about Intel but Xilinx has said that LVDS inputs will work just fine at 3.3V but the if you use the internal termination it not be accurate

Outputs won't work in the newer families because the faster LVDS transistors are disconnected about ~2.9V to protect them

Great, thanks! I only need inputs. I will give it a try.

[BrianHG]

Note that lying to Quartus, setting a fake IO voltage to get access to the differential LVDS input features will mean none of your final timing report can be considered valid.  Same with the precision of the LVDS characteristics listed in the Cyclone handbook.

[langwadt]

Note that lying to Quartus, setting a fake IO voltage to get access to the differential LVDS input features will mean none of your final timing report can be considered valid.  Same with the precision of the LVDS characteristics listed in the Cyclone handbook.

none of the timing report being valid seems a bit hyperbolic

[BrianHG]

Note that lying to Quartus, setting a fake IO voltage to get access to the differential LVDS input features will mean none of your final timing report can be considered valid.  Same with the precision of the LVDS characteristics listed in the Cyclone handbook.

none of the timing report being valid seems a bit hyperbolic

Ooops, sorry, your right my choice of words is overkill.  I mean regarding those IO in that bank in particular will present skewed results.

[Miti]

Note that lying to Quartus, setting a fake IO voltage to get access to the differential LVDS input features will mean none of your final timing report can be considered valid.  Same with the precision of the LVDS characteristics listed in the Cyclone handbook.

That would be for testing only. The final board will have the correct voltage.

[BrianHG]

Note that lying to Quartus, setting a fake IO voltage to get access to the differential LVDS input features will mean none of your final timing report can be considered valid.  Same with the precision of the LVDS characteristics listed in the Cyclone handbook.

That would be for testing only. The final board will have the correct voltage.

Just watch the temperature of the Cyclone.  If it stays cool, your ok.

[c64]

Since my development board has all VCCIOs connected to 3.3V, I wonder what happens if I assign 2.5V LVDS pairs but the bank is supplied by 3.3V. Is it going to blow up the chip, or is just the levels are messed up? I'm aware that all the I/Os in that bank must be 2.5V, otherwise Quartus will swear at me...

Interesting question, I would like to know as well. It might blow up, if comparators only support 2.5V or less

[langwadt]

Since my development board has all VCCIOs connected to 3.3V, I wonder what happens if I assign 2.5V LVDS pairs but the bank is supplied by 3.3V. Is it going to blow up the chip, or is just the levels are messed up? I'm aware that all the I/Os in that bank must be 2.5V, otherwise Quartus will swear at me...

Interesting question, I would like to know as well. It might blow up, if comparators only support 2.5V or less

it would be a really bad design if you could connect a legal 3.3V and then kill the IC by loading a bit file that use LVDS

[Miti]

Since my development board has all VCCIOs connected to 3.3V, I wonder what happens if I assign 2.5V LVDS pairs but the bank is supplied by 3.3V. Is it going to blow up the chip, or is just the levels are messed up? I'm aware that all the I/Os in that bank must be 2.5V, otherwise Quartus will swear at me...

Interesting question, I would like to know as well. It might blow up, if comparators only support 2.5V or less

it would be a really bad design if you could connect a legal 3.3V and then kill the IC by loading a bit file that use LVDS

I can't imagine that just by selecting wrong input type in Quartus, you can blow up a chip. I think the different blocks are all supplied at the same time, selection is done through some enable lines. My uneducated 2 cents.

[BrianHG]

You should be fine.  However, just remember, a larger VCCIO on any CMOS chip whose inputs sit in the middle threshold turns on 2 mosfets simultaneously at the input generating additional power supply current and heat unless it's a specifically engineered schmitt trigger input.

Being careful on 2-3 IO should allow you to get away with it.

Final results can only be guaranteed if you operate within the high&low confines of the DC electrical characteristics mentioned in the Cyclone Handbook.

I would personally drop the PLL chip in your other thread, do that inside the Cyclone and use a 74ALC04 or 74ALC245 to buffer the video into 2 bits & also pass the H&V sync through the cmos chip isolating and protecting the IOs on your FPGA from the scope you are connecting to as the 74ALC series has protection diodes at their inputs while the outputs will not drive the IO pins while the IC is powered down with the Cyclone.


Yes, powering up the source scope and feeding inputs into the Cyclone while it is powered off is potentially more of a problem than feeding inputs an odd differential signal within the range of VCCIO & GND.

[Miti]

Here it is. It works perfect. I loaded one of my FY6600 arbitrary slots with a signal that simulates the video signal, then I assigned two LVDS inputs to two 3.3V outputs inside the FPGA. With two programmable power supplies as negative inputs references set to 0.9V and 1.5V  and a long cable from the generator to the positive inputs, you can say by the amount of ringing, it works just perfect. No heating at all. If it works this well with lots of wires flapping in the wind, I'm sure it works even better on a board.

[BrianHG]

You're good to go!

[Miti]

Thank you all who helped me!