Author Topic: Cordic on verilog  (Read 3066 times)

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Offline den586Topic starter

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Cordic on verilog
« on: October 12, 2023, 02:31:36 pm »
Good time of day. Someone can share links or open sources to the Cordic algorithm on verilog, which would give out correctly SIN and COS depending on the incoming angle. I have modeled enough codes, and I have not found one whose output would coincide with the ideal SIN and COS within the limit of theoretical accuracy. Thank you in advance.
 

Offline BrianHG

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Re: Cordic on verilog
« Reply #1 on: October 12, 2023, 06:29:09 pm »
Did you do a forum search?

Maybe this code will help: https://www.eevblog.com/forum/fpga/vhdl-code-to-verilog-code/

Note that the final VHDL->Verilog translation I made all the way at the bottom of the thread works and you also get a modelsim setup comparing the original VHDL and Verilog versions.
 

Offline hamster_nz

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Re: Cordic on verilog
« Reply #2 on: October 12, 2023, 06:34:38 pm »
CORDIC is successive approximation. You should be able to get about 1 bit per iteration.

So for RF work you might implement it for 12 or 24 bits, for audio you might want 16 or 18 bits.

The other thing I that the input usually isn't in radians, so that can trip things up, along with the CODIC gain (the output can have a scale factor applied).
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Offline Someone

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Re: Cordic on verilog
« Reply #3 on: October 12, 2023, 10:56:46 pm »
The other thing I that the input usually isn't in radians, so that can trip things up
Unfortunately no cute name like Unit Turn, or Gradians:
https://en.wikipedia.org/wiki/Binary_angular_measurement
BAM
 
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Offline hamster_nz

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Re: Cordic on verilog
« Reply #4 on: October 12, 2023, 11:18:51 pm »
The other thing I that the input usually isn't in radians, so that can trip things up
Unfortunately no cute name like Unit Turn, or Gradians:
https://en.wikipedia.org/wiki/Binary_angular_measurement
BAM

Nice!.. that link introduced me to 'brads' (binary radians). It is such a cute term it has to stick. "I'm demodulating at a 80 million brads per second!"
« Last Edit: October 12, 2023, 11:20:58 pm by hamster_nz »
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline luudee

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Re: Cordic on verilog
« Reply #5 on: October 13, 2023, 08:41:33 am »

Hello,

please take a look on www.opencores.org, I believe we deposited there such an IP Core some time back ...

Best Regards,
rudi
 

Offline BrianHG

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Re: Cordic on verilog
« Reply #6 on: October 13, 2023, 12:21:08 pm »
System verilog version at opencores...

https://opencores.org/projects/cordic_atan_iq

Strangely looks familiar...
 

Offline den586Topic starter

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Re: Cordic on verilog
« Reply #7 on: October 13, 2023, 03:43:26 pm »
Thanks for the answers. You can give an answer. What accuracy can cordic provide if, for example, we have a 16-bit sine output, and 16 iterations? In theory, when arctangent coefficients are given, 16 arctanges (the last one) is arctg( 2^(-15) )= 0.001°. Does this mean we will have the maximum error of the 16-bit output sin(0.001°)*2^16?
 

Offline hamster_nz

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Re: Cordic on verilog
« Reply #8 on: October 14, 2023, 02:24:40 am »
If properly written it should be either the correct value or +/-  1 of the correct value.

There is a lot of subtly as to what the correct answer is. For example you may be more bothered about the outputs purity than its amplitude. A little rounding error can cause the + and - halves to both round towards zero, causing something like crossover distortion.

Or you might need the answer to be in the range of -32767 to +32767,  (0x8001 to 0x7FFF) so you have no DC bias in the output.

Oh, and should the transfer function be y = sin(x), or y=sin(x+1/(2^17)), as the input phase may have been rounded down as it was truncated to 16 bits.
« Last Edit: October 14, 2023, 06:26:27 am by hamster_nz »
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Online ali_asadzadeh

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Re: Cordic on verilog
« Reply #9 on: October 14, 2023, 10:46:33 am »
There is a gold mine in zipcpu website, actually I had found a bug in cordic design there, a few years ago, and have contacted Dan and he has updated the code,
check out his great article in here
https://zipcpu.com/dsp/2017/08/30/cordic.html
ASiDesigner, Stands for Application specific intelligent devices
I'm a Digital Expert from 8-bits to 64-bits
 
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