Electronics > FPGA

Correctly handling clocks on a older Cyclone IV

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Which pin is input clock connected to? Dedicated clock pin?

Try to run this as top level module. Don't use any PLL.

Check if clkOut is good 6M signal and check if cnt is correct

--- Code: ---module test
    input clk6,
    output clkOut,
    output cnt

reg [31:0] counter;
assign clkOut = clk6;
assign  cnt = counter;

always @(posedge clk6)
    counter <= counter + 1;


--- End code ---


This was going down to a rabbit hole and taking too much time so i did this:

--- Quote from: pieroc91 on June 01, 2023, 02:12:07 pm ---I'm also liking the route of coding a simple code that detects when clock changes and resets the counter of my clock divider so it syncs the divided clock to the external clock.

--- End quote ---

I made a very small routine that buffers the state of the 6mhz clock on the negative edge of the 66mhz clock and buffers that again on another register on the positive edge and compares them, if they don't match it means the 6mhz clock changed the state and generates a pulse, also with an AND makes it only generate that pulse on the change to low, this pulse is acting as a reset on the counter for the counter-made clock that proved the working state of all the rest of the code.

I tested if first with a push button and it worked flawlessly. The top signal is the 6mhz clock from the camera, the pulses on the second (not visible due to be much faster than my LA) and third is my corrected clock getting phase corrected.

Here's with the clock signal, now perfectly in phase, this time the pulses are visible, probably because of the sampling aliasing with the much faster signal.

Now is working perfectly... at least that part.

Thanks everyone that helped.


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