CPLD divide by 1.5 50% duty cycle

[perdrix]

OK all you CPLD mavens, I have a problem for which a CPLD is possibly a solution.

I need a physically small device with low pin count, VSSOP or TSSOP, and I want to convert a 15MHz input signal to 10MHz 50% duty cycle output.

So probably a divide by 3 with 50% duty cycle and a doubler, but there's likely a better way?

Initially I was thinking  ATF16V8BQL-15XU, but that has more inputs and outputs than I really need.

I have no previous experience of programming these beasts and only know of the tools by name (e.g. WinCUPL).

Thanks
David

[artag]

Rather than divide by 3 and multiply by 2, you probably want to multiply by two (delay and XOR) then divide by 3. Though you'll still end up with a mark-space ratio that's influenced by the difference between low-to-high propagation delay and high-to-low propagation delay, and the width of the doubler's delay.

Is that important ? It might be adjustable by messing with the offset of the input slicer, but I guess that will add some jitter.

[Kleinstein]

15 MHz to 10 MHz with 50% duty cycle is no possible with just logic. This would be more like something for a PLL, or maybe a synchronization of a 10 MHz oscillator.

[SiliconWizard]

Agree, if all you need your CPLD to do here is generate this clock output, use a specialized PLL IC. There are many out there.

If the CPLD could implement additional logic functions, then you could select a small FPGA instead (like in the Lattice iCE40/MachXO2/XO3 series, and there are similar small ones with other vendors), with a minimum number of logic cells, and just one embedded PLL. Cost would be pretty low. You'd use the embedded PLL for your clock output, and the available logic cells for anything else you might need now or in the future.

[daqq]

Well, the simplest/smallest solution might actually be an MCU. STM has a fair amount of small cheap ARMs. You could use for instance the STM32L011 in any of the packages (3x3mm QFN or the TSSOP14 package). The device acccepts a logic signal as a clock input, use the internal PLL to convert it to your desired freq and enable the master clock output, which will output the generated clock. Cheaper and simpler than a CPLD/FPGA, just add a cap or two.