Visualize the PCIe communication protocol

[TheGreatNed]

Hello,

I was wondering what the best way to visualize the PCIe protocol is. I know both Intel and Xilinx provide soft and hard ip for pcie drivers. However, these are closed source and I can only simulate their output -- not what goes on inside.

I would love to be able to see what a packet looks like before it enters the PHY and how it looks coming out of the PHY. Does anyone have any advice on using the pcie opencores or ip to achieve this?

Thank you

[Someone]

You can see those specific details in the simulations provided by Altera, Xilinx claim to have similar but I haven't looked too deeply at their example.

[asmi]

Find a PCI Express specification - it describes what signal looks like on a line, what packet looks like as it passes through the stack. It's conceptually very similar to how Ethernet works and it's OSI stack, except that PCIE has less layers because it's much more simple.

[KE5FX]

Take a look at https://github.com/enjoy-digital/litepcie and see if that helps.  Also http://www.xillybus.com/doc/xilinx-pcie-principle-of-operation is worth looking at.  Even though it's a commercial product its inner workings are well-described.

[tmbinc]

Not sure which layer you're mostly interested - if it's above PHY, then another way is to install a PCIe analyzer software (I like the Teledyne/Lecroy Summit one a lot, but there are different ones). They usually come with sample captures that work without hardware. It allows you to look at data on various levels, typically down to the bit level, and allows you to browse through TLPs.

PCIe is surprisingly sane.

The PHY "doesn't do a lot" from this perspective though - it's a SERDES with clock recovery. Perspective changes a lot of course once you look into the details.