Custom Spartan-7 FPGA board for beginners

[asmi]

bummer. this line destroyed what i'm about to reply on the above quote... long story short... for $100+ with step by step programming guide, that should be reasonable. i have $5 china altera fpga breakout laying for years and altera blaster bought separately, manually downloaded the fpga SW in many GB few years later (i dont even remember the name ) but dont have time to figure out how to start (namely the SW/VHDL/Verilog part), maybe due to lack of need, the toolchain maybe obsolete or invalidated by now. so they are unsolved puzzles. i need a puzzle that shows me how to solve it in quick time, like... this is the HW, this is the SW/IDE (download from <here>), you'll need this programmer, and this is the sample program, you compile it its surefire to do led blink. that kind of thing. i dont need another unsolved puzzle. good luck to you anyway. cheers.

Well that's the thing. Since I don't make any profit off this board, it makes no sense for me to even get involved into all these export shenanigans as that will not yield me anything except a lot of headaches. But then again - you will need to pass this "export check" in order to even download Vivado/Vitis IDE, and without it the board would be absolutely useless anyway.

[iMo]

There is a XC7A100T dev board with DDR3 from QMtech for about $80:
https://www.aliexpress.com/item/4000170003461.html
It's very hard to beat that if you buy parts at list price. There are also Zynq boards for even cheaper.

That is the key message any Maker outside China should remember.

[asmi]

I bit of a joke to lighten the mood:
Apparently US bureaucrats think that terrorists can't solder BGAs So if you can - you're not a terrorist     

[asmi]

There is a XC7A100T dev board with DDR3 from QMtech for about $80:
https://www.aliexpress.com/item/4000170003461.html
It's very hard to beat that if you buy parts at list price. There are also Zynq boards for even cheaper.

That is the key message any Maker outside China should remember.

The key message here is to do your research before you buy any board! It sucks in so many ways, but I'll just mention a couple - 1) it's main rail (Vccint) power supply can only provide up to 3 Amps of current, while the device can require up to double that current, 2) it's got NO peripherals at all.

[asmi]

Hmmm, I looked at my packing list, and it seems that the FPGA I used is not export-controlled (see screenshot)... Not sure what to make of it.

[Mechatrommer]

for beginner its not easy to assemble that BGA package FPGA and RAM. it will need advanced tools such as stencil or rework station. so trying to send 4 layer PCB to fab house (more expensive for small qty) is another matter, assembling them is another hard matter. for someone who only just learning to play/program with FPGA, i will be interested at reasonably priced ready made dev board + step by step on how to program it and what toolchains etc... do you think about selling it?

There is a XC7A100T dev board with DDR3 from QMtech for about $80:
https://www.aliexpress.com/item/4000170003461.html

It's very hard to beat that if you buy parts at list price. There are also Zynq boards for even cheaper. There is a lot of documentation available if you look it up.

oh yeah that thing actually exist. exactly what i was describing... thanks.

[c64]

Initially I was going to make just a bare minimum board without any peripherals, but soon realized that it won't be very useful. So I've added 256 Mbytes of DDR2 memory (128Mx16). The reason I've chosen DDR2 over DDR3 is that it allowed me to save one DC-DC converter because DDR2 uses the same 1.8 V rail that is used by the FPGA itself, while DDR3 uses 1.5 or 1.35 V.

Have you considered to just solder SO-DIMM connector, so if you need memory - you can just plug a DDR2 stick from laptop? One less BGA to solder

[asmi]

Have you considered to just solder SO-DIMM connector, so if you need memory - you can just plug a DDR2 stick from laptop? One less BGA to solder

SODIMMs have 64 bit data bus, while this board only uses (and really only has pins for) 16 bit, not to mention SODIMM connector is rather large so it would require larger PCB (==more expensive). To implement full 64 bit memory interface, I would need to use at least FGGA484 package, and these chips are quite a bit more expensive, not to mention it will require to design at least 6 layer board, also SODIMM modules consume quite a bit more power than a single chip, so I will need to beef up the DC-DC converter for the memory rail, which again flies in the face of my goal of avoiding dedicated power rail for the memory. So it comes full circle - I specifically wanted this board to be cheap in both PCB manufacturing and BOM cost so that more beginners would want to give it a try. You can use S25 device instead of S50 (the former is half the price of the latter), and use smallest 64 MByte DDR2 chip (which is about a quarter price of 256 MByte chip I used), so the whole thing will be about twice as cheap to assemble as mine was (I wanted to confirm max configuration works as this will guarantee that smaller ones will have no problems).
I'm thinking about designing a more complex board with something like DDR3 SODIMM for those who want a bit more ooumph for their designs, but it will be significantly more expensive to manufacture and assemble.

[c64]

Can you use only 16 bits and leave the rest unused? Not sure about power consumption though, probably it's not possible to disable refresh on unused chips.

SODIMM connector is less than 100mm long so it should fit onto the 100*100 board (which is the max size to get a good price from LCSC).

[Gerhard_dk4xp]

No, all the soldering "failures" I've had were because of too low temperature/inadequate reflow and were fixed by a second reflow. This has nothing to do with the chips. You just can NOT know if your BGA soldering was actually sufficient and when you do encounter bugs you have to do many copies to rule out soldering issues. This also doesn't address the lack of debugging access to pins, which makes it impossible to test fixes and requires a board respin for every change. It's impractical to have test points on every possible connection, which wouldn't be necessary on a QFP because you can attach bodge wires to the pins.

A customer of mine uses the curve tracer to check the functionality of the pin protection diodes.
That makes definitely sure that the soldering for the pin was a success.
OK, someone will now state the case of multiple parallel pins.

I'm playing with the idea of marrying a FPGA with GTX transceivers to a Beaglebone Black or AI.
That would separate the potential Linux problems/support and DDRn from my soldering art and
would let me concentrate on these fast JESD-204B ADCs, DACs and SDR.

I'm still stuck at the point wether I can get peripherals in the FPGA memory mapped
to a window in the ARM address space.
There must be a 16 bit multiplexed bus possible at least, but I have never seen it used.
The FPGA configuration could be bit banged by the BBB directly from a .bit file, no need for a dongle.

Cheers, Gerhard
 

[asmi]

Can you use only 16 bits and leave the rest unused? Not sure about power consumption though, probably it's not possible to disable refresh on unused chips.

SODIMM connector is less than 100mm long so it should fit onto the 100*100 board (which is the max size to get a good price from LCSC).

I don't quite see what advantages would SODIMM have over current solution - even if all technical issues were somehow resolved. I seriously doubt that SODIMM connector + module combination would cost less than just a single chip, and it would certainly be more cumbersome to use. What all these troubles are for?

[Bassman59]

No, all the soldering "failures" I've had were because of too low temperature/inadequate reflow and were fixed by a second reflow. This has nothing to do with the chips. You just can NOT know if your BGA soldering was actually sufficient and when you do encounter bugs you have to do many copies to rule out soldering issues. This also doesn't address the lack of debugging access to pins, which makes it impossible to test fixes and requires a board respin for every change. It's impractical to have test points on every possible connection, which wouldn't be necessary on a QFP because you can attach bodge wires to the pins.

Ya know, it's funny, I work at a small company ( < 50 people) and we solder BGAs to boards every day. Our most common sizes are the 256- and 484-ball jobs. Since we've been doing this for, oh, 20 years now, we have it ironed out and BGA attachment is not a problem.

Yes, that long experience helps. But if you simply say that it'll never work and you don't try, your prophecy fulfills itself.

[NorthGuy]

I don't quite see what advantages would SODIMM have over current solution - even if all technical issues were somehow resolved. I seriously doubt that SODIMM connector + module combination would cost less than just a single chip, and it would certainly be more cumbersome to use. What all these troubles are for?

SODIMM DDR3 is dirt cheap - compare prices to what you pay for ICs. The connector is probably $3-5 which will give you up to 16 G. The 16G module is under $100 now.

[asmi]

SODIMM DDR3 is dirt cheap - compare prices to what you pay for ICs. The connector is probably $3-5 which will give you up to 16 G. The 16G module is under $100 now.

No it won't. Take a look at schematics, and you will see why.

[dmendesf]

You stole my joke!   

I bit of a joke to lighten the mood:
Apparently US bureaucrats think that terrorists can't solder BGAs So if you can - you're not a terrorist     

[c64]

I don't quite see what advantages would SODIMM have over current solution - even if all technical issues were somehow resolved. I seriously doubt that SODIMM connector + module combination would cost less than just a single chip, and it would certainly be more cumbersome to use. What all these troubles are for?

Connector can be found for < $1
OK maybe no advantages for you. But I see few advantages for others:
- one less BGA to solder
- easy to upgrade/downgrade
- most people probably already have some spare memory modules

[asmi]

Connector can be found for < $1

Where?

OK maybe no advantages for you. But I see few advantages for others:
- one less BGA to solder

I don't see it as advantage, especially since one of the goals of this board was to practice BGA soldering.

- easy to upgrade/downgrade

What's the reason for that?

- most people probably already have some spare memory modules

I don't have any

But you're missing the bigger picture - for SODIMM you will need to add a dedicated DC-DC converter (existing one is only rated for 1.5 A, and Vccaux can consume up to 0.6 A of that depending on your design), and once you do that you might as well go for DDR3 instead (the sole reason I went for DDR2 was to avoid adding another DC-DC rail for memory, all else being equal, DDR3 wins every time - less power, faster speed, more capacity, cheaper), you will also need to add a termination controller (which is not required for bare chips). This will also expose another problem, which I alluded to in my previous post - insufficient amount of ADDR/CTRL pins in FPGA bank to route all SODIMM address lines - normally you'd need 3 memory byte lanes for that, but since I only have a single bank, I can only dedicate 2 memory lanes for ADDR/CTRL. And I still don't know how to "terminate" unused data lines - couldn't find any information on that in memory's datasheet.

That said, since design is an open source design, you are more than welcome to take it, remove the memory chip (and any other things you don't need) and add your memory connector to see if you can get it all to work. I don't have high hopes for that because of everything I said above, but I'd love to be proven wrong.

[c64]

Forgive me if I say something stupid, I have no experience with SDRAM whatsoever. But SODIMM has multiple chips and if you only use one of them, all the others will not consume any power. Yes it will be a waste of chips, but if module is free - no problem

Regarding insufficient amount of lines in FPGA - do you need to use all the lines from the module? And if the module contains same chip as you currently use, will it have same number of address lines?

Regarding termination controller - i don't know what it is but sounds scary. 

Connector can be found for < $1

Where?

In China 

[kmike]

Dear asmi,

first of all thank you for your great work!

Is there a constraint file available? I dont know wich IO standard to use for the DDR RAM pins

thanks!

br,
mike

[asmi]

Dear asmi,

first of all thank you for your great work!

Is there a constraint file available? I dont know wich IO standard to use for the DDR RAM pins

thanks!

br,
mike

When you create a memory controller using MIG, it will assign proper constraints automatically. Just make sure you get pinout right (exactly like on schematics). If my memory serves me (no pun intended), MIG uses SSTL18_II standard for single-ended signals (with 50 Ohm ODT for bidirectional signals), and DIFF_SSTL18_II for differential ones.
I've attached a xdc file (rename the file and remove  the ".txt" extension because forum doesn't allow xdc files) which you can load into MIG to save you time for manual entry of all signals, but I'm not 100% sure that is accurate, so please verify that pin assignments are correct. If you install smaller capacity memory chip than what I did, drop the highest address line(s) as necessary.
As for the rest of it, please note that user buttons are connected to the same IO bank as memory, so you will need to use LVCMOS18 standard. HDMI data/clock pins use TMDS_33 standard, everything else is LVCMOS33 (unless you customize the board and/or connect something to IO bank 14 which uses a different standard).

[kmike]

Thank you!

do you clock the DDR chip with 333MHz?

br,
mike

[asmi]

Thank you!

do you clock the DDR chip with 333MHz?

br,
mike

Yes, that's the maximum clock rate for this package. I feed 166.667 MHz and 200 MHz clocks into MIG, which are generated by the "Clocking" IP from the system clock of 100 MHz.

[kmike]

Thank you!

do you clock the DDR chip with 333MHz?

br,
mike

Yes, that's the maximum clock rate for this package. I feed 166.667 MHz and 200 MHz clocks into MIG, which are generated by the "Clocking" IP from the system clock of 100 MHz.

Just to make sure, that this horse is dead, 166.667 MHz goes to the system clock of the MIG and 200 MHz is the reference clock?
I need an additional 10MHz clock in my design, should I generate it with the clocking IP or the MIG? Vivado keeps telling me that my internal reset is not in sync with the clk_ui of the MIG...

[asmi]

Just to make sure, that this horse is dead, 166.667 MHz goes to the system clock of the MIG and 200 MHz is the reference clock?
I need an additional 10MHz clock in my design, should I generate it with the clocking IP or the MIG? Vivado keeps telling me that my internal reset is not in sync with the clk_ui of the MIG...

I've attached the diagram which shows the correct clocking. Note that reset polarity for clocking IP needs to be changed to active-low as that's how the sysreset signal is wired on a board. It also shows 10 MHz output I've added for you.
For reset, ui_clk_sync_rst is a reset signal (sysreset) synchronized to ui_clk. But if you need a reset for your 10 MHz blocks, you will need to synchronize sysreset to it. You can use Processor System Reset IP for that, or do you manually in HDL.

[kmike]

Thank you!

Got it finally sorted out. Vivado automatically puts an AXI clock converter into the AXI interconnect (if I have different clocks in the design), but always(!) assigns 100MHz to to master interface, even if I use 83MHz CPU clock...
Solution is to put a clock converter manually at each AXI slave, that is running on a different clock than the CPU. Looks like automation cannot solve everything 

Br,
mike