Custom Spartan-7 FPGA board for beginners

[asmi]

Just for the heck of it, I decided to try loading Linux on this board. It turned out to be harder than I expected, as u-boot's compilation fails when the system is configured without network support (as the board doesn't contain any network hardware). The workaround is to force network support on in u-boot even if it's disabled in a kernel.
Anyways, I got Linux to boot successfully. I've connected external UART-USB module as this way I can use terminal like putty, as opposed to jtagterminal function of xsdb as the latter is more limited. The full bootlog is here for those curious:

Code: [Select]

U-Boot 2020.01 (Dec 05 2020 — 14:15:39 +0000)

Model: Xilinx MicroBlaze
DRAM: 256 MiB
WDT: Not found!
Loading Environment from SPI Flash... Invalid bus 0 (err=-19)
*** Warning — spi_flash_probe_bus_cs() failed, using default environment

In: serial
Out: serial
Err: serial
Model: Xilinx MicroBlaze
Net: Net Initialization Skipped
No ethernet found.
U-BOOT for sp50

Hit any key to stop autoboot: 0
U-Boot>?
? — alias for 'help'
askenv — get environment variables from stdin
base — print or set address offset
bdinfo — print Board Info structure
boot — boot default, i.e., run 'bootcmd'
bootd — boot default, i.e., run 'bootcmd'
bootelf — Boot from an ELF image in memory
bootm — boot application image from memory
bootp — boot image via network using BOOTP/TFTP protocol
bootvx — Boot vxWorks from an ELF image
cmp — memory compare
coninfo — print console devices and information
cp — memory copy
crc32 — checksum calculation
dhcp — boot image via network using DHCP/TFTP protocol
dm — Driver model low level access
echo — echo args to console
editenv — edit environment variable
env — environment handling commands
exit — exit script
ext2load — load binary file from a Ext2 filesystem
ext2ls — list files in a directory (default /)
ext4load — load binary file from a Ext4 filesystem
ext4ls — list files in a directory (default /)
ext4size — determine a file's size
false — do nothing, unsuccessfully
fatinfo — print information about filesystem
fatload — load binary file from a dos filesystem
fatls — list files in a directory (default /)
fatsize — determine a file's size
fdt — flattened device tree utility commands
fsinfo — print information about filesystems
fsload — load binary file from a filesystem image
fsls — list files in a directory (default /)
fstype — Look up a filesystem type
go — start application at address 'addr'
gpio — query and control gpio pins
help — print command description/usage
iminfo — print header information for application image
imxtract — extract a part of a multi-image
interrupts- enable or disable interrupts
irqinfo — print information about IRQs
itest — return true/false on integer compare
led — manage LEDs
ln — Create a symbolic link
load — load binary file from a filesystem
loadb — load binary file over serial line (kermit mode)
loads — load S-Record file over serial line
loadx — load binary file over serial line (xmodem mode)
loady — load binary file over serial line (ymodem mode)
loop — infinite loop on address range
ls — list files in a directory (default /)
md — memory display
mii — MII utility commands
mm — memory modify (auto-incrementing address)
mw — memory write (fill)
nfs — boot image via network using NFS protocol
nm — memory modify (constant address)
part — disk partition related commands
ping — send ICMP ECHO_REQUEST to network host
printenv — print environment variables
pxe — commands to get and boot from pxe files
reset — Perform RESET of the CPU
run — run commands in an environment variable
save — save file to a filesystem
saveenv — save environment variables to persistent storage
saves — save S-Record file over serial line
setenv — set environment variables
sf — SPI flash sub-system
showvar — print local hushshell variables
size — determine a file's size
sleep — delay execution for some time
source — run script from memory
sspi — SPI utility command
sysboot — command to get and boot from syslinux files
test — minimal test like /bin/sh
tftpboot — boot image via network using TFTP protocol
true — do nothing, successfully
version — print monitor, compiler and linker version
U-Boot>version
U-Boot 2020.01 (Dec 05 2020 — 14:15:39 +0000)

microblazeel-xilinx-linux-gcc (GCC) 9.2.0
GNU ld (GNU Binutils) 2.32.0.20190204
U-Boot>boot
## Booting kernel from Legacy Image at 80000000 ...
Image Name: Linux-5.4.0-xilinx-v2020.2
Image Type: MicroBlaze Linux Kernel Image (uncompressed)
Data Size: 9085444 Bytes = 8.7 MiB
Load Address: 80000000
Entry Point: 80000000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 82e00000 ...
Image Name: petalinux-image-minimal-microbla
Image Type: MicroBlaze Linux RAMDisk Image (uncompressed)
Data Size: 6930085 Bytes = 6.6 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at 81e00000
Booting using the fdt blob at 0x81e00000
Loading Kernel Image
Loading Ramdisk to 8e964000, end 8efffea5 ... OK
Loading Device Tree to 8e95d000, end 8e963193 ... OK

Starting kernel ...

Ramdisk addr 0x8e964000,
FDT at 0x8e95d000
earlycon: uartlite_a0 at MMIO 0x40600000 (options '115200n8')
printk: bootconsole [uartlite_a0] enabled
cma: Reserved 16 MiB at 0x8d800000
Linux version 5.4.0-xilinx-v2020.2 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 PREEMPT Fri Dec 4 04:46:15 UTC 2020
setup_memory: max_mapnr: 0x10000
setup_memory: min_low_pfn: 0x80000
setup_memory: max_low_pfn: 0x90000
setup_memory: max_pfn: 0x90000
Zone ranges:
DMA [mem 0x0000000080000000-0x000000008fffffff]
Normal empty
HighMem empty
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000080000000-0x000000008fffffff]
Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff]
setup_cpuinfo: initialising cpu 0
setup_cpuinfo: Using full CPU PVR support
wt_msr_noirq
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists, mobility grouping on. Total pages: 64960
Kernel command line: console=ttyUL0,115200 earlycon root=/dev/ram0 rw
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 228324K/262144K available (5400K kernel code, 177K rwdata, 1456K rodata,
167K init, 564K bss, 17436K reserved, 16384K cma-reserved, 0K highmem)
Kernel virtual memory layout:
* 0xfffea000..0xfffff000 : fixmap
* 0xff800000..0xffc00000 : highmem PTEs
* 0xff7ff000..0xff800000 : early ioremap
* 0xf0000000..0xff7ff000 : vmalloc & ioremap
rcu: Preemptible hierarchical RCU implementation.
Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
irq-xilinx: /amba_pl/interrupt-controller@41200000: num_irq=4, sw_irq=0, edge=0x9
xilinx_timer_init: Timer base: 0xf0020000, Clocksource base: 0xf0020010
clocksource: xilinx_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604467 ns
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns
/amba_pl/timer@41c00000: irq=1, cpu_id 0
xilinx_timer_shutdown
xilinx_timer_set_periodic
Calibrating delay loop... 48.74 BogoMIPS (lpj=243712)
pid_max: default: 4096 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
rcu: Hierarchical SRCU implementation.
devtmpfs: initialized
random: get_random_u32 called from bucket_table_alloc.isra.0+0x70/0x218 with crng_init=0
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 16 (order: -4, 448 bytes, linear)
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic allocations
audit: initializing netlink subsys (disabled)
audit: type=2000 audit(0.350:1): state=initialized audit_enabled=0 res=1
clocksource: Switched to clocksource xilinx_clocksource
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 256 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 2048 (order: 1, 8192 bytes, linear)
TCP bind hash table entries: 2048 (order: 3, 40960 bytes, linear)
TCP: Hash tables configured (established 2048 bind 2048)
UDP hash table entries: 128 (order: 0, 6144 bytes, linear)
UDP-Lite hash table entries: 128 (order: 0, 6144 bytes, linear)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
random: fast init done
Freeing initrd memory: 6764K
workingset: timestamp_bits=14 max_order=16 bucket_order=2
Key type cifs.idmap registered
romfs: ROMFS MTD (C) 2007 Red Hat, Inc.
io scheduler mq-deadline registered
io scheduler kyber registered
XGpio: gpio@40000000: registered, base is 510
XGpio: gpio@40000000: dual channel registered, base is 504
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
40600000.serial: ttyUL0 at MMIO 0x40600000 (irq = 4, base_baud = 0) is a uartlite
printk: console [ttyUL0] enabled
printk: console [ttyUL0] enabled
printk: bootconsole [uartlite_a0] disabled
printk: bootconsole [uartlite_a0] disabled
brd: module loaded
loop: module loaded
spi-nor spi0.0: s25fl128l (16384 Kbytes)
4 fixed-partitions partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000220000 : "fpga"
0x000000220000-0x0000002a0000 : "boot"
0x0000002a0000-0x0000003a0000 : "bootenv"
0x0000003a0000-0x0000009a0000 : "kernel"
libphy: Fixed MDIO Bus: probed
NET: Registered protocol family 17
Key type encrypted registered
Freeing unused kernel memory: 164K
This architecture does not have kernel memory protection.
Run /init as init process
INIT: version 2.88 booting
mount: mounting proc on /proc failed: Device or resource busy
mount: mounting sysfs on /sys failed: Device or resource busy
/etc/rcS.d/S04mdev: line 10: /proc/sys/kernel/hotplug: No such file or directory
Sat Dec 5 14:17:57 UTC 2020
random: dd: uninitialized urandom read (512 bytes read)
Configuring packages on first boot....
(This may take several minutes. Please do not power off the machine.)
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
Removing any system startup links for run-postinsts ...
/etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... Cannot find device "eth0"
Starting Dropbear SSH server: random: dropbearkey: uninitialized urandom read (32 bytes read)
Generating 2048 bit rsa key, this may take a while...
random: dropbearkey: uninitialized urandom read (32 bytes read)
random: crng init done
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQC7Ixdq8q05F/6974vKDs6onvP/35jPb0e3LdkOUDFp
Q64CGJVgww1sJj9MacLYlRNIqmt5dDtoHE5MHjQTJG4yyaIXO072xVGiUz9bPJKwXxy/loVMYDLeJbGH
7cLW85DQh9isR4CDgnRJzYRV0he6FMTKmLRcb+7FLhHOQ8LCDAZqf1St114LXqK54Qzbpy+7k+tTLqK8
QUSXys5ad52WzzYhRArUYO/78NLPXSYsjciULBGnmaqnC2Yfp2ls3M+KiAYvVuzgSr1B6iIgPdIoY0iH
ulkn8qS/Vz2JWFYKZs5CYa35X39ZukreVGc3mjpmzyi6h9Ws6PaXdb2btMG7 root@sp50
Fingerprint: sha1!! fe:ab:fb:e7:42:2d:13:d8:ae:8d:cf:9e:d0:0f:b8:ab:e7:1b:e4:1c
dropbear.
Starting internet superserver: inetd.
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2020.2 sp50 /dev/ttyUL0

sp50 login: root
Password:
root@sp50:~# uname -a
Linux sp50 5.4.0-xilinx-v2020.2 #1 PREEMPT Fri Dec 4 04:46:15 UTC 2020 microblaze GNU/Linux
root@sp50:~# uname -a
Linux sp50 5.4.0-xilinx-v2020.2 #1 PREEMPT Fri Dec 4 04:46:15 UTC 2020 microblaze GNU/Linux
root@sp50:~#

Now I'm thinking it would be cool to design a small addon board with 100 Mbit ethernet PHY and a UART-USB bridge - there should be just enough GPIOs to do that, and 100 Mbit PHY uses MII bus running at 25 MHz, so lack of length-matching should not be a big deal.
Right now I'm booting everything through JTAG as the system as-built does not fit into 128 Mbit QSPI flash device I have installed on a board. I think it's possible to cut away enough fat to make it fit, or alternatively it's possible to replace the flash with 256 Mbit device in the same SOIC-8 package.
Also Xilinx recently added experimental support of SMP into petalinux, would be interesting to see if I can get it to work. I've created a dual-core design, and it fits into S50 device I have on a board along with 128K of L2 cache (implemented using System Cache IP).

[SiliconWizard]

I didn't know MicroBlaze was supported by Linux (but I've never used it, so it's just that I didn't know!)

[asmi]

I didn't know MicroBlaze was supported by Linux (but I've never used it, so it's just that I didn't know!)

Linux support was initially implemented by the company PetaLogix (hence the name - "PetaLinux"), but it was acquired by Xilinx back in 2012.
I think Antel's NIOS is also supported by Linux, though as far as I remember only for paid versions as free version lacks MMU.

[DiTBho]

What do you need to implement in order to support SMP or AMP?
Is there an IP, or do you have to manually implement code?

[asmi]

What do you need to implement in order to support SMP or AMP?
Is there an IP, or do you have to manually implement code?

Since this support is experimental, there is next to zero official (or unofficial) documentation, and the code will not even compile as-is if you turn on SMP, so you will need to make some code changes to make the build work.

As for system design, from what I've been able to gather, it requires identical Linux-grade cores with ACE for their I/D buses, all connected to a System Cache IP instance which works as a unified L2 cache for all cores, you also need a dedicated interrupt controller and dedicated timer for each core, and also a single "global" timer for entire system, and all of that is on top of regular requirements for some kind of non-volatile memory (QSPI being the typical example), a minimum of 32 MB of RAM, and some kind of UART or network interface, so you can actually interact with the system. All peripherals needs to be connected to a single peripheral bus accessible to all CPU cores. Also as interrupt assignment to individual cores is not implemented yet, all PICs need have all interrupts wired the same way.

Here is the link to relevant commit to official petalinux github repository: https://github.com/Xilinx/linux-xlnx/commit/17cbc3a2e0bebb8c0fe7d5ae060e3412fd1a0be6 As it's all is very experimental, be prepared to dive in head first into the source code and debug things.

[asmi]

Just in case anyone is interested - I've designed a little addon board with 100 Mbps Ethernet PHY and USB-UART bridge (because using mdm's uart submodule is not very convenient with Linux shell). Like the main board, the source files are in my github rep, and the license is WTFPL , so feel free to do what you want with it. And as is typical of me, I've screwed up the first revision by mixing up USB D+ and D- lines , but the second revision works like charm, and it works in petalinux (tested in version 2020.2) as well as in lwip stack for baremetal applications (tested using lwip-echo sample in Vitis 2020.2 using the same bitstream that I used for petalinux build) because I use the same PHY chip as Arty board (I've done this exactly to minimize a chance for some kind of incompatibility).

[rstofer]

for someone who only just learning to play/program with FPGA, i will be interested at reasonably priced ready made dev board + step by step on how to program it and what toolchains etc... do you think about selling it?

There are literally hundreds of boards, some with better reference material than others.
I picked a board designed for university classes even though I know there are cheaper boards because of the Reference Material.

https://reference.digilentinc.com/reference/programmable-logic/basys-3/start?redirect=1

See in the list where it talks about "Getting Started With Vivado"?  This is a very friendly introduction for newcomers.  There is a link to installing Vivado as a separate page.

Digilent has terrific documentation but their boards are expensive.  You could start with the Lattice IceStick and follow the instructions at VHDLwhiz.com.  It is definitely inexpensive:

https://www.mouser.com/new/lattice-semiconductor/lattice-icestick-kit/

NandLand.com has an inexpensive board but I haven't tried it:

https://www.nandland.com/goboard/index.html

There seems to be plenty of documentation.

Here's an interesting company with a number of boards.  I have a couple of the 2.01 boards and the Debug adapter board.

https://www.ztex.de/usb-fpga-2/

The OP's board is another possibility if he gets to production quantities.  It's nice to have a built-in forum at eevBlog

[NorthGuy]

Just in case anyone is interested - I've designed a little addon board with 100 Mbps Ethernet PHY and USB-UART bridge

No pictures?

[asmi]

No pictures?

Here you go It's not very interesting - just two chips (PHY and USB-UART) and some support components.
FPGA die temperature hovers around 60°C when Linux is running, so heatsink is definitely required to prevent it from overheating.

[asmi]

Oh - one more thing. Since I got some blank PCBs for both the main board and that addon, if someone wants to make one for himself, pls let me know and I can ship a board for free (you cover shipping). PCBs are from JLCPCB, so the soldermask is not very durable, but you shouldn't have too much trouble assembling it using hot air gun and soldering iron. You will need a microscope though, as 0201 are too damn small to even see with naked eyes, even if you have a very good vision.
I can probably ship an assembled one too, but only in Canada as I don't want to deal with export BS at this point as QSPI flash device I use is export-controlled (yea, I was surprised to find this out - FPGA itself is EAR99, but the freaking flash chip is not ). I still don't have PnP machine, so don't expect fast shipping as I will be assembling to order - well unless someone orders like few 100's of them so I will have to see into some mass-production options

[PointyOintment]

I might be interested if not for the fact that I already have a Xilinx FPGA board (Papilio Duo) sitting around unused. That's probably the case for a lot of people here.

How is the heatsink attached? It looks like a clip that mechanically attaches to the board, but I don't see any holes in the board in the pictures in the first post.

[asmi]

How is the heatsink attached? It looks like a clip that mechanically attaches to the board, but I don't see any holes in the board in the pictures in the first post.

It's attached to the BGA package itself. Here is the mounting mechanism: https://www.qats.com/Heat-Sink/superGRIP  The specific heatsink I use is this one: ATS-X50150G-C1-R0 It's not cheap, but it ships with all mounting hardware, requires minimal PCB space (~5mm around BGA package), no holes, only takes a few seconds to mount, and the mounting is reversible, meaning you can remove the heatsink without destroying anything.

[gnuarm]

Oh - one more thing. Since I got some blank PCBs for both the main board and that addon, if someone wants to make one for himself, pls let me know and I can ship a board for free (you cover shipping). PCBs are from JLCPCB, so the soldermask is not very durable, but you shouldn't have too much trouble assembling it using hot air gun and soldering iron. You will need a microscope though, as 0201 are too damn small to even see with naked eyes, even if you have a very good vision.
I can probably ship an assembled one too, but only in Canada as I don't want to deal with export BS at this point as QSPI flash device I use is export-controlled (yea, I was surprised to find this out - FPGA itself is EAR99, but the freaking flash chip is not ). I still don't have PnP machine, so don't expect fast shipping as I will be assembling to order - well unless someone orders like few 100's of them so I will have to see into some mass-production options

The Avnet web page says the part is ECCN: 3A991.D.  I've always had trouble figuring this stuff.  The government docs are inscrutable.  The only reliable source of info is the vendors that I can see.

The odd thing is the requirement in that section is "Field programmable logic devices having a maximum number of single-ended digital input/outputs between 200 and 700".  So a 196 pin package would not apply.  Maybe they count the I/Os on the die as it is easy to repackage a die i expect.  But when I look up 3A991.d it refers to column AT1 in the CCL Country Chart which is entirely empty!  Why have a classification that has no restrictions?  Are there other restrictions? 

The other category this might fit is 3A001.a.7 which is for devices with more than 700 I/Os, so again not a match and again a reference to column AT1, the null set. 

So far I've been safe with my products because I supply to a networking company who doesn't want to go to jail when they ship their products with my board inside.  Actually, their electronics is much more advanced, but apparently covered by the same rules. 

[asmi]

The Avnet web page says the part is ECCN: 3A991.D.  I've always had trouble figuring this stuff.  The government docs are inscrutable.  The only reliable source of info is the vendors that I can see.

On DK website, where I actually bought the device I'm using, it's listed as EAR99: https://www.digikey.ca/en/products/detail/xilinx-inc/XC7S50-2FTGB196C/8040781
But in general - this is exactly why I don't want to deal with export controls. I though about doing a Kickstarter for a few FPGA projects, but when I realized the amount of bureaucracy I will have to go through to ship internationally, I decided that it was more than I was prepared to handle 

[gnuarm]

At one time I had to ship my product to Mexico where my customer assembles their systems.  What a huge PITA!  I tried filing the paper work myself to save the $10 FedEx wanted, but only once!  Everything about using the government web site is a big hassle.  Just generating a password was ridiculous.  They had some seven or eight rules and I followed them all.  It said I didn't do it right, I had to include special characters.  Try again, no, not THAT special character.  Try again, no, not THAT special character either, here's the list of what you can use.  Try again, no, you aren't doing it right!!!  No explanation.  Turns out their list of special characters was not correct.  Then you had to change it every 30 days which means I had to write it down, which is a no-no for security actually.  Then once I got locked out of the account because I didn't change it in time I had to speak to someone to get back in and that took two freaking days to get someone on the phone!!!   

I gladly paid FedEx their $10 from then on. 

My customer ended up with a different assembler who had me ship to Laredo, TX and they trucked it across the border.  I gave them the whatever it's called number for the product once and they never bothered me about it again.  Ahhhh!   

[gnuarm]

Do you have a list of the design rules you used on this board?  I want to consider using the 196 pin package and want to get some pricing from my assembly house.  I'm not sure what solder mask rules to use among others.

[BrianHG]

No pictures?

Here you go It's not very interesting - just two chips (PHY and USB-UART) and some support components.
FPGA die temperature hovers around 60°C when Linux is running, so heatsink is definitely required to prevent it from overheating.

Funny, you seem to have compensated for the length of trace between the IC U2 and your connector, but it doesn't seem to take into account the odd length of the traces on the Sparta board to it's connector.

[asmi]

Funny, you seem to have compensated for the length of trace between the IC U2 and your connector, but it doesn't seem to take into account the odd length of the traces on the Sparta board to it's connector.

I did length matched them on a main board too (see rev D) and even manufactured these boards, but it turned out that was unnecessary for MII interface. Now I'm thinking maybe I should attempt 1G RGMII with rev D...

[asmi]

Do you have a list of the design rules you used on this board?  I want to consider using the 196 pin package and want to get some pricing from my assembly house.  I'm not sure what solder mask rules to use among others.

This board was designed around JLCPCB's 4 layer process (as the absolute cheapest way to get 4 layer boards with controlled impedance) and their JLC2313 stackup as more suitable for high-speed designs (thinner prepreg allows for thinner traces for the same impedance), but I didn't go all the way down to 0.09 mm traces, rather the smallest traces/spacings on the board are 0.1 mm. I use 0.2 mm hole/0.45 mm pad vias. As for soldermask, I have set 0.05 mm clearance and 0.1 mm min width, and that seemed to work OK.

[gnuarm]

Do you have a list of the design rules you used on this board?  I want to consider using the 196 pin package and want to get some pricing from my assembly house.  I'm not sure what solder mask rules to use among others.

This board was designed around JLCPCB's 4 layer process (as the absolute cheapest way to get 4 layer boards with controlled impedance) and their JLC2313 stackup as more suitable for high-speed designs (thinner prepreg allows for thinner traces for the same impedance), but I didn't go all the way down to 0.09 mm traces, rather the smallest traces/spacings on the board are 0.1 mm. I use 0.2 mm hole/0.45 mm pad vias. As for soldermask, I have set 0.05 mm clearance and 0.1 mm min width, and that seemed to work OK.

I find JLC's web page on capabilities to be unclear.  That's why I asked.  When I've tried asking the current assembly house about this they always say they will build whatever I give them.  lol   They don't seem to get into the specs department.   I'll try asking them what they can build cheaply and see if their pwb house can come up with specs.

[asmi]

I find JLC's web page on capabilities to be unclear.  That's why I asked.  When I've tried asking the current assembly house about this they always say they will build whatever I give them.  lol   They don't seem to get into the specs department.   I'll try asking them what they can build cheaply and see if their pwb house can come up with specs.

If your PCB fab can do 0.1/0.1 mm traces/spacings, 0.2/0.45mm vias, controlled impedance and the right stackup, you will be good to go. I recommend you to not dwell too much on a soldermask, as it's not super-critical here, and in my experience fabs which can match or exceed the geometry requirements we're talking about here, will have good enough soldermask process to successfully assemble boards. Stackup is super-important to get correct impedances, if you will have to use a different one, you will need to adjust all CI traces' width (which are DDR2 and HDMI on this board) to match whatever width your stackup requires to achieve 50 Ohm single-ended/100 Ohm differential impedance.
And this is why nowadays designing a "fab-agnostic" board is almost impossible for anything high-speed. Thankfully, quite a bit of fabs are willing to manufacture boards to your stackup specs as long as you didn't spec materials which either don't exist (for example speccing out a prepreg sheets of thickness which doesn't actually exist), or hard to source. Some won't even charge extra for custom stackup - like WellPCB, which is my fab of choice for production boards, as well as prototypes for 6 layers and above.

[gnuarm]

It's easy to say "don't worry about it", but if I am asking for a quote I need to give them a spec.  It's not like I have a board laid out they can measure from.  That's ok.  I have the Xilinx numbers and have derived values from that.  I was just looking for some confirmation.

[asmi]

It's easy to say "don't worry about it", but if I am asking for a quote I need to give them a spec.  It's not like I have a board laid out they can measure from.  That's ok.  I have the Xilinx numbers and have derived values from that.  I was just looking for some confirmation.

Well if cheap Chinese fabs nowadays have no trouble manufacturing 0.05 mm solder mask expansion and 0.1 mm wide slivers, whatever fab you use should be able to do that too. Or just order them at JLCPCB and call it a day. I avoid using them for production runs (like I said, I prefer WellPCB, they are a bit more expensive, but offer significantly higher quality), but for 4 layer prototypes they are great.

[gnuarm]

It's easy to say "don't worry about it", but if I am asking for a quote I need to give them a spec.  It's not like I have a board laid out they can measure from.  That's ok.  I have the Xilinx numbers and have derived values from that.  I was just looking for some confirmation.

Well if cheap Chinese fabs nowadays have no trouble manufacturing 0.05 mm solder mask expansion and 0.1 mm wide slivers, whatever fab you use should be able to do that too. Or just order them at JLCPCB and call it a day. I avoid using them for production runs (like I said, I prefer WellPCB, they are a bit more expensive, but offer significantly higher quality), but for 4 layer prototypes they are great.

I don't buy bare PWB.  I buy assembled boards.  That's why I was looking for specs to give to them rather than asking what they can do.  They can do whatever I ask them to do, they just use an appropriate PWB fabricator.  If I want a quote, I give them my specs.

They are presently building my board at a very good price.  I don't want to screw that up by asking them to build a board they will have to use a different service with. 

Also, I don't know what JLC can or can't do.  Their capabilities page is complex and ill defined with many errors in the illustrations.  Not what I think of as a bench mark of any kind.

[nockieboy]

@asmi - just wondering, did you place the DDR2 further away from the FPGA in the PCB for a reason?  Looks like it could have been placed a lot closer?