Cyclone IV GX EP4CGX22 LVDS pins

[pinout_1]

Hello,

I need to use high-speed LVDS pins on the EP4CGX22 FPGA.  Now I am completely confused which pins I can use as high-speed LVDS pins.  What is 14/14 highlighted in yellow in the product table? I found the information, that any port cannot be used for high speed LVDS. (https://catherineh.github.io/programming/2016/11/08/picking-lvds-pins-on-the-de0-nano)

I tried to use pin planner for this fpga which is in the Quartus Prime Lite, however, I did not know any additional info about the high-speed ports.  I also found information about tcl scripting for pin assigments.  But I have no idea how I can apply it to the desired result.

The question would be how can I find out which LVDS ports I can use as high speed (840 Mbps)?

Thank you very much for the answers.

[mattselectronics]

Have a look at this document:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/ep4cgx22.pdf

DIFFIO_ sould be what you are searching for.
Which package are you using?

[pinout_1]

Thanks for the answer, mattselectronics.

Yes, I saw this table. I think that these Fast-mode LVDS should be somehow separated or marked. But now it's just ordinary IO ports.

I'm using FBGA-324 package with 1330 logic array blocks.

[asmi]

Use Xilinx 7 series FPGA instead They don't have this BS, all differential pairs over there are equal and any one can go up to 1250 Mbps for speed grade -2 and -3 officially, and ~1500 Mbps unofficially - the tool will complain, but won't stop you from generating a bitstream and programming device.

[Scrts]

One more thing: what will be the purpose? Because LVDS can be used for different standards and protocols as well as different voltage/current levels.

[mattselectronics]

If you want to use the LVDS pins with 840Mbps, you need to use this IP-Core:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf

I'm no expert on Cyclone IV, because it is pretty old now. As far as I remember, there is no specialized SERDES hardware on Cyclone IV devices. So maybe all LVDS pins could work?

Maybe the Cyclone 10 LP documentation could point you into the right direction, because it is basically a optimized Version of the cyclone iv without gigabit transceivers.

[Daixiwen]

The Cyclone IV GX does have hardware transceivers, on the left side of the package, that can do between 600Mbps and 2.5Gbps. Those are dedicated pins that can only be used for that. They are called transceivers or XCVR in Altera's documentation. The EP4CGX22 has 4 TX and 4 RX such pairs, and if you have a look at the pinout file they are at the beginning of the list (GXB_*). To use those pins you need to go through the Megawizard, either one already existing for your specific prototol, or the ALTGX Megawizard for generic purposes.
The GX22 also has generic LVDS pairs, similar to the ones on the EP4CE22 on the DE0 nano, that can use a softcore SERDES. You will find them in the pin list with the names DIFFIO_B*. Those pins are slower than the transceivers, and if I'm not mistaken their performance depend on their position so you need to be careful. But for 840Mbps you will need to use the tranceivers anyway, those generic LVDS pins can only reach 200-300 Mbps.

[BrianHG]

those generic LVDS pins can only reach 200-300 Mbps.

This is for the CycloneIV -E devices...

All the generic DFFIO  'LVDS_E_3R' pins can do 550/640MB/s depending on speed grade.  The 'True' 'LVDS' pins can do 640/740/840MB/s depending on speed grade.  They all work with the altlvds_rx/tx.  The true LVDS are available on the left and right sides of the FPGA while the emulated LVDS_E_3R pins are everywhere.

The true LVDS allow you to program series and parallel termination inside the FPGA.  The emulated require external terminator resistors.

If you select 'LVDS' IO standard for an IO, when compiling, if you use an illegal pair of pins, or clock it too high, it wont compile.

For the CycloneIV-GX devices, you have access to the dedicated transceivers which can do the high multi-GB/s.
They have similar features to the True-LVDS ports plus extra clock reconstruction capabilities when using the more powerful dedicated LVSD megafunction instead of the regular one. (I think.)

[pinout_1]

Hello,

Thanks everyone for the answers,

If you want to use the LVDS pins with 840Mbps, you need to use this IP-Core:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf

I'm no expert on Cyclone IV, because it is pretty old now. As far as I remember, there is no specialized SERDES hardware on Cyclone IV devices. So maybe all LVDS pins could work?

Maybe the Cyclone 10 LP documentation could point you into the right direction, because it is basically a optimized Version of the cyclone iv without gigabit transceivers.

I think exactly the same. I come to the idea that I can use any LVDS on this FPGA. I found several projects on the Github, which use general purpose ports in particular.

One more thing: what will be the purpose? Because LVDS can be used for different standards and protocols as well as different voltage/current levels.

The main purpose would be to achieve MIPI CSI-2.

Use Xilinx 7 series FPGA instead They don't have this BS, all differential pairs over there are equal and any one can go up to 1250 Mbps for speed grade -2 and -3 officially, and ~1500 Mbps unofficially - the tool will complain, but won't stop you from generating a bitstream and programming device.

Sorry, but now I have no options to use Xilinx FPGAs.

[Scrts]

One more thing: what will be the purpose? Because LVDS can be used for different standards and protocols as well as different voltage/current levels.

The main purpose would be to achieve MIPI CSI-2.

Is it for image sensor? 4 Lanes? Be sure it's capable of continuous clock output, otherwise it's a nightmare. What's the rate per lane?

[pinout_1]

One more thing: what will be the purpose? Because LVDS can be used for different standards and protocols as well as different voltage/current levels.

The main purpose would be to achieve MIPI CSI-2.

Is it for image sensor? 4 Lanes? Be sure it's capable of continuous clock output, otherwise it's a nightmare. What's the rate per lane?

Yes, for the OV9281 image sensor, but with 2 lanes. It can provide continuous clock output. Would be very good to reach the maximum possible MIPI data rate. Now, typical MIPI data rate of the sensor declared as 800Mbps @ 2-Lane.

[mattselectronics]

All the generic DFFIO  'LVDS_E_3R' pins can do 550/640MB/s depending on speed grade.  The 'True' 'LVDS' pins can do 640/740/840MB/s depending on speed grade.  They all work with the altlvds_rx/tx.  The true LVDS are available on the left and right sides of the FPGA while the emulated LVDS_E_3R pins are everywhere.

Do you know, wher Intel wrote that down?
I wasn't able to read that out of the documents I found....

[BrianHG]

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf

CycloneIV handbook.
Page 477, both true and emulated LVDS speed limits are on that page.
My quoted numbers are accurate and correct.

If you are using one-way transmit for a simple signal like HDMI, we have achieved 1080mbps on the emulated port using a -C8 rated at 550mbps over here: https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/  The true LVDS is still preferred.

You would need the GX transceivers for 1485mb/s needed for 1080p@60Hz.

[mattselectronics]

Ah, OK and this little footnote then tells us, which pins are the true LVDS and which arn't:

Cyclone IV GX—true LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6.

Well, that couldn't be more clear and easy to find 

[Scrts]

Yes, for the OV9281 image sensor, but with 2 lanes. It can provide continuous clock output. Would be very good to reach the maximum possible MIPI data rate. Now, typical MIPI data rate of the sensor declared as 800Mbps @ 2-Lane.

Is 120FPS really needed? Can sensor support that at full frame? OVT is known not to support full frame rate at full resolution - only full rate at lower resolutions.

If 60FPS at full resolution is enough, then:
1280H * 800V * 1.15(assuming 15% blanking) * 60FPS * 10bpp / 2 lanes = 353Mbps/lane