Your simulation doesn't seem to be doing anything at all.
In your test-bench, are you generating any signals, like a basic clock?
The sim should be counting up time in the status bar until you click stop, or your testbench code generates a $stop or $end.
This is what the key portion of my TB looks like:
localparam period = 500000000/CLK_KHZ_IN ;
logic [2:0] phase_cs;
logic phase_step,phase_updn;
logic phase_done;
// *********************************************************************************************
// This module generates the master reference clocks for the entire memory system.
// *********************************************************************************************
BrianHG_DDR3_PLL #(.FPGA_VENDOR (FPGA_VENDOR), .INTERFACE_SPEED (INTERFACE_SPEED), .DDR_TRICK_MTPS_CAP (DDR_TRICK_MTPS_CAP),
.CLK_KHZ_IN (CLK_KHZ_IN), .CLK_IN_MULT (CLK_IN_MULT), .CLK_IN_DIV (CLK_IN_DIV),
.DDR3_WDQ_PHASE (DDR3_WDQ_PHASE), .DDR3_RDQ_PHASE (DDR3_RDQ_PHASE)
) DUT_DDR3_PLL ( .RST_IN (RST_IN), .RST_OUT (RESET), .CLK_IN (CLK_IN), .DDR3_CK (DDR3_CLK),
.DDR3_CLK_WDQ (DDR3_CLK_WDQ), .DDR3_CLK_RDQ (DDR3_CLK_RDQ), .CMD_CLK (CMD_CLK), .PLL_LOCKED (PLL_LOCKED),
.phase_cs ( phase_cs ), .phase_step ( phase_step ), .phase_updn ( phase_updn ),
.phase_sclk ( CLK_IN ), .phase_done ( phase_done ) );
// ******************************************************************************************************
// This module receives the commands from the multi-port ram controller and sequences the DDR3 IO pins.
// ******************************************************************************************************
BrianHG_DDR3_PHY_SEQ #(.FPGA_VENDOR (FPGA_VENDOR), .FPGA_FAMILY (FPGA_FAMILY), .INTERFACE_SPEED (INTERFACE_SPEED),
.CLK_KHZ_IN (CLK_KHZ_IN), .CLK_IN_MULT (CLK_IN_MULT), .CLK_IN_DIV (CLK_IN_DIV),
.DDR3_CK_MHZ (DDR3_CK_MHZ), .DDR3_SPEED_GRADE (DDR3_SPEED_GRADE), .DDR3_SIZE_GB (DDR3_SIZE_GB),
.DDR3_WIDTH_DQ (DDR3_WIDTH_DQ), .DDR3_NUM_CHIPS (DDR3_NUM_CHIPS), .DDR3_NUM_CK (DDR3_NUM_CK),
.DDR3_WIDTH_ADDR (DDR3_WIDTH_ADDR), .DDR3_WIDTH_BANK (DDR3_WIDTH_BANK), .DDR3_WIDTH_CAS (DDR3_WIDTH_CAS),
.DDR3_WIDTH_DM (DDR3_WIDTH_DM), .DDR3_WIDTH_DQS (DDR3_WIDTH_DQS), .DDR3_ODT_RTT (DDR3_ODT_RTT),
.DDR3_RZQ (DDR3_RZQ), .DDR3_TEMP (DDR3_TEMP), .DDR3_WDQ_PHASE (DDR3_WDQ_PHASE),
.DDR3_RDQ_PHASE (DDR3_RDQ_PHASE), .DDR3_MAX_REF_QUEUE (DDR3_MAX_REF_QUEUE), .IDLE_TIME_uSx10 (IDLE_TIME_uSx10),
.POWR_UP_TIMER_uS (POWR_UP_TIMER_uS), .BANK_ROW_ORDER (BANK_ROW_ORDER),
.PORT_VECTOR_SIZE (PORT_VECTOR_SIZE), .PORT_ADDR_SIZE (PORT_ADDR_SIZE)
) DUT_PHY_SEQ ( // *** DDR3_PHY_SEQ Clocks & Reset ***
.RST_IN (RESET), .DDR_CLK (DDR3_CLK), .DDR_CLK_WDQ (DDR3_CLK_WDQ), .DDR_CLK_RDQ (DDR3_CLK_RDQ),
// *** DDR3 Ram Chip IO Pins ***
.DDR3_RESET_n (DDR3_RESET_n), .DDR3_CK_p (DDR3_CK_p), .DDR3_CKE (DDR3_CKE), .DDR3_CS_n (DDR3_CS_n),
.DDR3_RAS_n (DDR3_RAS_n), .DDR3_CAS_n (DDR3_CAS_n), .DDR3_WE_n (DDR3_WE_n), .DDR3_ODT (DDR3_ODT),
.DDR3_A (DDR3_A), .DDR3_BA (DDR3_BA), .DDR3_DM (DDR3_DM), .DDR3_DQ (DDR3_DQ),
.DDR3_DQS_p (DDR3_DQS_p), .DDR3_DQS_n (DDR3_DQS_n), .DDR3_CK_n (DDR3_CK_n),
// *** Command port input ***
.SEQ_CMD_CLK (CMD_CLK), .SEQ_CMD_ENA_t (SEQ_CMD_ENA_t), .SEQ_WRITE_ENA (SEQ_WRITE_ENA),
.SEQ_ADDR (SEQ_ADDR), .SEQ_WDATA (SEQ_WDATA), .SEQ_WMASK (SEQ_WMASK),
.SEQ_RDATA_VECT_IN (SEQ_RDATA_VECT_IN), .SEQ_refresh_hold (SEQ_refresh_hold),
// *** Command port results ***
.SEQ_BUSY_t (SEQ_BUSY_t), .SEQ_RDATA_RDY_t (SEQ_RDATA_RDY_t), .SEQ_RDATA (SEQ_RDATA),
.SEQ_RDATA_VECT_OUT (SEQ_RDATA_VECT_OUT), .SEQ_refresh_queue (SEQ_refresh_queue),
// *** Diagnostic flags ***
.SEQ_CAL_PASS (SEQ_CAL_PASS), .DDR3_READY (DDR3_READY) );
// ***********************************************************************************************
//************************************************************************************************************************************************************
//*** DDR3 Verilog model from Micron Required for this test-bench.
//************************************************************************************************************************************************************
`include "ddr3.v"
//************************************************************************************************************************************************************
//*** DDR3 Verilog model from Micron Required for this test-bench.
//*** The required DDR3 SDRAM Verilog Model V1.74 available at:
//*** [url]https://media-www.micron.com/-/media/client/global/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip?rev=925a8a05204e4b5c9c1364302de60126[/url]
//*** From the 'DDR3 SDRAM Verilog Model.zip', only these 2 files are required in the main simulation test-bench source folder:
//*** ddr3.v
//*** 4096Mb_ddr3_parameters.vh
//************************************************************************************************************************************************************
// component instantiation
ddr3 sdramddr3_0 (
.rst_n ( DDR3_RESET_n ),
.ck ( DDR3_CK_p[0] ),
.ck_n ( DDR3_CK_n[0] ),
.cke ( DDR3_CKE ),
.cs_n ( DDR3_CS_n ),
.ras_n ( DDR3_RAS_n ),
.cas_n ( DDR3_CAS_n ),
.we_n ( DDR3_WE_n ),
.dm_tdqs ( DDR3_DM ),
.ba ( DDR3_BA ),
.addr ( DDR3_A ),
.dq ( DDR3_DQ ),
.dqs ( DDR3_DQS_p ),
.dqs_n ( DDR3_DQS_n ),
.tdqs_n ( ),
.odt ( DDR3_ODT )
);
//************************************************************************************************************************************************************
//************************************************************************************************************************************************************
//************************************************************************************************************************************************************
logic [7:0] WDT_COUNTER; // Wait for 15 clocks or inactivity before forcing a simulation stop.
logic WAIT_IDLE = 0; // When high, insert a idle wait before every command.
localparam int WDT_RESET_TIME = 255; // Set the WDT timeout clock cycles.
localparam int SYS_IDLE_TIME = WDT_RESET_TIME-64; // Consider system idle after 12 clocks of inactivity.
localparam real DDR3_CK_MHZ_REAL = CLK_KHZ_IN * CLK_IN_MULT / CLK_IN_DIV / 1000 ; // Generate the DDR3 CK clock frequency.
localparam real DDR3_CK_PERIOD = 1000 / DDR3_CK_MHZ_REAL ; // Generate the DDR3 CK period in nanoseconds.
initial begin
WDT_COUNTER = WDT_RESET_TIME ; // Set the initial inactivity timer to maximum so that the code later-on wont immediately stop the simulation.
SEQ_CMD_ENA_t = 0 ;
SEQ_WRITE_ENA = 0 ;
SEQ_ADDR = 0 ;
SEQ_WDATA = 0 ;
SEQ_WMASK = 0 ;
SEQ_RDATA_VECT_IN = 0 ;
SEQ_refresh_hold = 0 ;
phase_cs = 3'b000 ;
phase_step = 1'b0 ;
phase_updn = 1'b0 ;
RST_IN = 1'b1 ; // Reset input
CLK_IN = 1'b0 ;
#(50000);
RST_IN = 1'b0 ; // Release reset at 50ns.
while (!PLL_LOCKED) @(negedge CMD_CLK);
execute_ascii_file(TB_COMMAND_SCRIPT_FILE);
end
always #period CLK_IN = !CLK_IN; // create source clock oscillator
always @(posedge CLK_IN) WDT_COUNTER = (SEQ_BUSY_t!=SEQ_CMD_ENA_t) ? WDT_RESET_TIME : (WDT_COUNTER-1'b1) ; // Setup a simulation inactivity watchdog countdown timer.
always @(posedge CLK_IN) if (WDT_COUNTER==0) begin
Script_CMD = "*** WDT_STOP ***" ;
$stop; // Automatically stop the simulation if the inactivity timer reaches 0.
end
As you can see, I define a clock period and have my PLL, DDR3_PHY_SEQencer & Micron's ddr3.v wired together.
Then at initialize, I set the power-up defaults.
Then I wait for the PLL lock.
Then I execute my command script, (you may ignore this)
Then, at 'always #period CLK_IN = !CLK_IN; // create source clock oscillator' I am synthesizing the clock.
The next 2 lines, I am counting clock cycles and if there is no activity on the DDR3 sequencer command for enough clock cycles, I tell the simulator to $stop. At this point, the simulation waveform is viewable.
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