Electronics > FPGA

DDR3 initialization sequence issue

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promach:

--- Quote --- use that DCM to output 1 tunable 256 step phase from the clock you are receiving from the PLL.
--- End quote ---

cool, but how to phase-shift to the middle of DQ bit once the first DQ bit transition edge is detected ?

Besides, I suppose the transition edge detection should not be done using FPGA fabric ?


When I simulate my design with DCM, I have Warning : Input Clock Period Jitter on instance test_ddr3_memory_controller.ddr3_control.pll_ddr.dcm_sp_inst exceeds 1.000 ns. Locked CLKIN Period = 0.822. Current CLKIN Period = 0.822. ?

Why PLL DCM could not be locked ?





promach:
Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency?



promach:
I have solved the locked issue above.

Now, I have this Warning : Please wait for PSDONE signal before adjusting the Phase Shift issue.  Why ?

BrianHG:

--- Quote from: promach on August 06, 2021, 01:53:23 pm ---I have solved the locked issue above.

Now, I have this Warning : Please wait for PSDONE signal before adjusting the Phase Shift issue.  Why ?



--- End quote ---

Phase shifting is like changing the PLL settings, so you need to wait for the new PLL lock.
Though, the step is so small, the PLL moves smoothly.

This takes a few clock cycles with Altera PLLs as well.

promach:

--- Quote ---Phase shifting is like changing the PLL settings, so you need to wait for the new PLL lock.
Though, the step is so small, the PLL moves smoothly.

This takes a few clock cycles with Altera PLLs as well.
--- End quote ---

Xilinx requires only a single clock cycle to wait for the new PLL lock

However, ck_dynamic waveform is not really locked to udqs_r even though lock_dynamic is asserted high.  WHY ?

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