tRP is the time between a PRECHARGE and an ACTIVATE. Where is your PRECHARGE after the write. Or, if you are using AUTO-PRECHARGE, then you need to assume where the AUTO-PRECHARGE took place and call that the beginning time for the tRP. Remember, you are ACTIVATING a new row in BANK 0 where you came from a previous row in BANK 0. You need to PRECHARGE the old bank first. Without the precharge, you may activate a different BANK where you did, but if you are going this route, make sure your ram controller can keep track of which banks are each individually doing what and when as you will occasionally need different precharges at different places.
Note that in my code, I'm use 100% manual precharge with smart recognition of what banks are doing what to allow random access across banks for flexibility. If you want raw throughput speed, but no bank management, you may per-engineer your sequence for the optimal command placement to run non-stop through all the banks and close one behind the other knowing that your reads will always be in straight line instead of the optimal read/write scatter capability in my controller which was designed to adapt to X&Y graphics burst and copy/fill commands. (IE, The raster width address spacing Y coordinates are each on the next adjacent bank.)
Take a look at my attached image. (See figure 90)
I have an:
ACTIVATEh'0000,B#1 0ns
WRITE BL8 +14ns
WRITE BL8 +8ns (2 consecutive WRITE BL8s)
time to last written byte +20ns
PRECHARGE B#1 +16ns this is tWR. (If you are using AUTO-PRECHARGE, this is where it will be, though your not sending the command, it is happening internally in the DDR3.)
ACTIVATEh'0400,B#1 +14ns this is tRP, time between AUTO-PRECHARGE to ACTIVATE.
This is completely different than a read. The PRECHARGE is permitted even before the read data is returned. (See figure 72) If you go the complex route like my controller, you will need to analyze the next instruction coming in before even the current one is going out to know if the precharge is needed, or there is and access in the same row or different bank to achieve the best possible command sequence minimizing wait states.
Your sim looks like you used the read command timing with AUTO-PRECHARGE to ACTIVATE for a write command. Also, your write command appears to have way too many cycles.