wait, it is the turning on of dynamic phase shift option of the PLL that actually caused the maximum frequency limit to drop from 400MHz to 374.5MHz.

Then you can only do 375 MHz.

And since dynamic phase shift option is needed, so I could not have 8:1 (no 400MHz for me), this is why I am only having 7:1 (350MHz)

Any frequency can be divided by 8 (or by 4, or by any other number). 375/8 = 46.875 MHz, or 375/4 = 93.75 MHz, or 375/2 = 187.5 MHz. Take your pick and create the corresponding clock. Abandon your oscillator clock for anything except for PLL feed.

again, I am confused as in why **use 4:1 serializer, it will require 100 MHz slow clock** ?

The X:1 serializer will require 375/X frequency. On the IO side you have 375 Mb/s. On the fabric side you have X wires - the data gets spread over these wires, so each wire carriers 375/X Mb/s.

When you connect two of such serializers to an ODDR or IDDR, you get double data rate outside of FPGA - 375*2 = 750 Mb/s. Between IDDR/ODDR and serializers, the signal is carried by two wires (D0 and D1), each carrying 375 Mb/s. On the fabric side you get 2*X wires (each of the two serializers has X wires). Each wire carries 750/(2*X) = 375/X Mb/s = 375/X MHz.

So, if you want two 4:1 serializers (X = 4), your slow clock must be 375/X = 375/4 = 93.75 MHz

If you want two 2:1 serializers (X = 2), your slow clock must be 375/X = 375/2 = 187.5 MHz

If you abandon serializers, and only use ODDR/IDDR (X = 1), your slow clock must be 375/X = 375/1 = 375 MHz, which is the same as ODDR/IDDR clock.