Author Topic: DDR3 initialization sequence issue  (Read 49112 times)

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Offline promach

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Re: DDR3 initialization sequence issue
« Reply #525 on: September 10, 2021, 05:02:07 pm »
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Say, if you want 350 MHz fast clock, create 700 MHz VCO (your 50 MHz crystal multipled by 14), then divide by 2 to get 350 MHz clock, by 4 to get 175 MHz clock, or by 8 to get 87.5 MHz clock.

why do you even need to generate 700MHz ?
 

Online NorthGuy

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Re: DDR3 initialization sequence issue
« Reply #526 on: September 10, 2021, 05:15:41 pm »
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Say, if you want 350 MHz fast clock, create 700 MHz VCO (your 50 MHz crystal multipled by 14), then divide by 2 to get 350 MHz clock, by 4 to get 175 MHz clock, or by 8 to get 87.5 MHz clock.

why do you even need to generate 700MHz ?

VCO must be between 400 and 1080 MHz for your speed grade. If you want to get 350 MHz from the PLL, you need to use either 700 or 1050 MHz VCO.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #527 on: September 10, 2021, 05:17:25 pm »
Which exact Xilinx document did you see such VCO specification ?
 

Online NorthGuy

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Re: DDR3 initialization sequence issue
« Reply #528 on: September 10, 2021, 05:42:51 pm »
Which exact Xilinx document did you see such VCO specification ?

The datasheet - ds162.
 
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Offline promach

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Re: DDR3 initialization sequence issue
« Reply #529 on: September 11, 2021, 02:23:47 am »
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #530 on: September 11, 2021, 03:17:14 am »
Use my toggle logic.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #531 on: September 11, 2021, 03:17:57 am »
What do you exactly mean by toggle logic ?
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #532 on: September 11, 2021, 03:25:24 am »
On the read clock, when each BL8 128bit has been latched, toggle a DFF.
On the read clock, delay that toggle output DFF by 1 clock.
Remember, the read clock is 400MHz, so during an uninterrupted continuous burst, that toggle DFF will invert every 4 clocks.

On your 400MHz ck_0 clock, latch the 128bit when that 1-delayed-toggle has flipped.
Also, on the ck_0 clock, DFF latch that 1-delayed-toggle as well.

Now, feed all that ck_0 bulk into your slower clock domain and by the slower clock domain's clock, capture the data when is sees the ck_0 toggle output has flipped.
Also generate a BL8_read_data_ready when that capture has been done.
« Last Edit: September 11, 2021, 03:27:38 am by BrianHG »
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #533 on: September 11, 2021, 03:32:39 am »
Read my 'BrianHG_DDR3_IO_PORT_ALTERA.sv' v1.00, lines 535-575.

Please read around my added manual generated 2+1 to 1 fan-out buffers.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #534 on: September 11, 2021, 03:36:24 am »
I feel that 'BrianHG_DDR3_IO_PORT_ALTERA.sv' v1.00, lines 535-575 is conceptually similar to Multi-cycle path (MCP) formulation with feedback.

Please correct me if wrong.

What do you exactly mean by added manual generated 2+1 to 1 fan-out buffers. ?

By the way, why are you not using asynchronous FIFO instead ?
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #535 on: September 11, 2021, 03:47:51 am »
My solution us unidirectional.  All I have done is make the 'toggle' a next data valid signal which is slow enough so that it is impossible to miss on the slower clock domain unless that clock is slower than 1:4 as the BL8 will run too fast to keep up with unless you insert NOP commands with the read burst.

That added 1 clock delay ensures the random phase of the 128 read bit read buffers which may arrive +/-1 clock to the next domain depending on routing, since the read wont be 0 degrees, that the ck_0 acknowledge will only register after the rest of the 128 bits have all arrived at their destination.

The fanout buffer aid is for large DDR3 configurations, like 512bit BL8 reads.  I broke the latch enable into 2 banks so that with 1 control in, I get 2 outs so that those data latch enables only feed the clock enable on half the data bits instead of all 512.  1 DFF feeding 512 inputs is a heavy capacitive load on the FPGA fabric and will cut into FMAX.  The +1 is the separate toggle delay feeding my slower 200MHz clock domain so that no route from the first 2 banks of 256 bits enable signals will not need to share seeding the full 512 enable signals in my 200MHz domain.  This helps optimize routing of that separate data valid toggle closer where it needs to be in the slower clock domain.
« Last Edit: September 11, 2021, 04:01:13 am by BrianHG »
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #536 on: September 11, 2021, 03:54:39 am »
Altera's Async FIFOs max out at 315MHz for a -6 and 238MHz for a -8.  My home made DFF SCFIFO maxes out at ~472MHz on a -6 and ~402MHz on a -8.  My core runs at 400MHz, so I cannot use Altera's FIFOs unless I use a 4:1 fifo on the pins instead of my current 2:1.  IE, my FIFO would have to be 64bit in, 128 bit out instead of the current 32bit in and 128bit out.

My logic is compatible with Altera, Lattice, Xilinx, Gowin...
« Last Edit: September 11, 2021, 05:16:34 am by BrianHG »
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #537 on: September 11, 2021, 04:08:32 am »
What do you mean by SCFIFO and 4:1 fifo ?
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #538 on: September 11, 2021, 04:18:16 am »
Altera's SCFIFO function is their synchronous clock fifo which uses their core ram blocks instead of logic cells.
If I used 3 of those at 3 strategic points in my design, my DDR3 controller would be well under 1K logic elements, but, I would also use 3 ram blocks.

Well as for the 4:1, well, if the IO data is running at 800Mbps, the normal 2:1 DDRIO would require a fifo's input running at 400MHz 32 bit wide for a 16bit DDR3.  If my DDRIO was running in 4:1 mode instead, the fifo's input side will need to run at 200MHz with 64bits for a 16bit DDR3.

You could say I can use the Altera FIFO with a speed grade of -6 running the ram at 300MHz with the normal 2:1 DDR input.  But not anywhere near 400MHz or even be overclock-able to 500MHz.
« Last Edit: September 11, 2021, 04:30:23 am by BrianHG »
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #539 on: September 11, 2021, 07:47:13 am »
I believe what you meant by 4:1 fifo is actually 4:1 serializer which is a term more commonly used by me and @NorthGuy

Please correct me if wrong.
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #540 on: September 11, 2021, 08:27:34 am »
The DDRIO I describe is my primary 2:1 and 1:2 serializer.  In your case, you are saying that you are using a 4:1 and 1:4 DDRIO?  I know Lattice has these as they are called a ?DDROUT/IN2x?

My code after the DDRIO 1:2 / 2:1 is my software second serializer which accumulates the BL8 into single 128bit parallel chunk.  This is the part of my code which I have been referencing.  It is a secondary home-made 1:4 deserializer with a correction ability to re-align to the first read preamble if needed.
« Last Edit: September 11, 2021, 10:04:47 am by BrianHG »
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #541 on: September 11, 2021, 05:04:34 pm »
Yes, I am using 4:1 serializer and 1:4 deserializer.

I have just a made a github commit coding modification to use 350MHz / 4 = 87.5MHz clk_serdes as the "slow" clock domain.

However, I found that the simulation waveform for both data_in_oserdes_0 and data_in_oserdes_1 signals which are the input for 4:1 serializers should be updated 90 degrees in advance of clk_serdes domain.

Note: these 2 signals are driven by test_data inside clk_serdes domain

Do I have some easier countermeasure solution than creating a clk_serdes_270 domain which has a 90 degree phase lead of clk_serdes domain ?

 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #542 on: September 12, 2021, 11:01:36 am »
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #543 on: September 17, 2021, 01:03:21 pm »
For https://github.com/promach/DDR , I have at least solved most of the simulation issues inside Xilinx ISIM simulator.

Now, I could not simulate the actual Micron simulation model inside Xilinx ISIM simulator because it does not accept some systemverilog syntax inside Micron model.

Do you guys have any suggestions other than modifying the Micron model itself ?
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #544 on: September 17, 2021, 11:37:33 pm »
Try setting Xilinx preferred default language syntax to SystemVerilog, or rename Micron's .v to a .sv.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #545 on: September 18, 2021, 02:14:57 am »
Xilinx ISE does not support systemverilog
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #546 on: September 18, 2021, 04:16:31 am »
I think a more possible workaround is to use Vivado due to systemverilog support limitation of Xilinx ISE tool.

So, need to migrate ODDR2 and PLL dynamic phase shift primitives

What do you guys think ?
 

Online NorthGuy

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Re: DDR3 initialization sequence issue
« Reply #547 on: September 18, 2021, 01:12:24 pm »
I think a more possible workaround is to use Vivado due to systemverilog support limitation of Xilinx ISE tool.

So, need to migrate ODDR2 and PLL dynamic phase shift primitives

What do you guys think ?

Vivado doesn't support Spartan-6.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #548 on: September 18, 2021, 01:13:36 pm »
Simulation is different from bitstream generation.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #549 on: September 23, 2021, 01:13:31 pm »
Why do I have tIS violation inside the following Vivado simulation ?

 


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