Electronics > FPGA

DDR3 initialization sequence issue

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BrianHG:
The DDRIO I describe is my primary 2:1 and 1:2 serializer.  In your case, you are saying that you are using a 4:1 and 1:4 DDRIO?  I know Lattice has these as they are called a ?DDROUT/IN2x?

My code after the DDRIO 1:2 / 2:1 is my software second serializer which accumulates the BL8 into single 128bit parallel chunk.  This is the part of my code which I have been referencing.  It is a secondary home-made 1:4 deserializer with a correction ability to re-align to the first read preamble if needed.

promach:
Yes, I am using 4:1 serializer and 1:4 deserializer.

I have just a made a github commit coding modification to use 350MHz / 4 = 87.5MHz clk_serdes as the "slow" clock domain.

However, I found that the simulation waveform for both data_in_oserdes_0 and data_in_oserdes_1 signals which are the input for 4:1 serializers should be updated 90 degrees in advance of clk_serdes domain.

Note: these 2 signals are driven by test_data inside clk_serdes domain

Do I have some easier countermeasure solution than creating a clk_serdes_270 domain which has a 90 degree phase lead of clk_serdes domain ?

promach:
Solved using this code modification commit

promach:
For https://github.com/promach/DDR , I have at least solved most of the simulation issues inside Xilinx ISIM simulator.

Now, I could not simulate the actual Micron simulation model inside Xilinx ISIM simulator because it does not accept some systemverilog syntax inside Micron model.

Do you guys have any suggestions other than modifying the Micron model itself ?

BrianHG:
Try setting Xilinx preferred default language syntax to SystemVerilog, or rename Micron's .v to a .sv.

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