Author Topic: DDR3 initialization sequence issue  (Read 49109 times)

0 Members and 1 Guest are viewing this topic.

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #575 on: September 25, 2021, 03:56:29 am »
Quote
Now, to get the maximum tIS and tIH out of the FPGA outputs, you would target the transition of all command and address lines on the CK# transition.  This is not ck_270.

Let's back up a bit.

ck_270 is 90 degree phase ADVANCE/LEAD , not phase LAG.

and therefore ck_270 will be able to center the command inputs bits to the posedge of ck, and at the same time trivially satisfies tIS requirement.
 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #576 on: September 25, 2021, 03:58:18 am »
 :palm:  Your CK_0 is the DDR3 CK, the DDR3 CK# would be your CK_180.
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #577 on: September 25, 2021, 03:59:59 am »
yes you are right, and my code actually already adhered to what you just mentioned.

I suppose my coding is just too long for you to inspect more carefully.

Please correct me if I miss anything.
 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #578 on: September 25, 2021, 04:03:18 am »
and therefore ck_270 will be able to center the command inputs bits to the posedge of ck, and at the same time trivially satisfies tIS requirement.

'Satisfies' so long as all your FPGA outputs switch fast enough within the specified period, which also become a interface IO timing issue when you want to change system frequencies.

This will also make board trace timing crucial for all the control lines, it will make them just as sensitive to length matching as DQS and DQ making routing a nightmare for your controller.  The control lines were supposed to be the easiest to route having such a large timing clearance that you can go almost double length, or have more ram chips driven in parallel adding load capacitance without worries.
 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #579 on: September 25, 2021, 04:05:10 am »
I would say give it a rest and just invert the CK output to your DDR3 and run all your logic internally on CK_0 like the way I have it.
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #580 on: September 25, 2021, 04:08:25 am »
May I know why use ck instead of ck_270 ?

I do not get what you meant by implication of routing nightmare in your reply post just above.

Note: ck_obuf is similar to ck

 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #581 on: September 25, 2021, 04:15:20 am »
Please zoom and time these 2 points in the vertical red line for me.
I assume you are running at 350MHz.
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #582 on: September 25, 2021, 04:47:12 am »
I think I should use ck_180 instead of ck_270 to drive the command inputs.

See below the timing differences as requested by you.

Note: Vivado simulator seems to have only 1 cursor



 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #583 on: September 25, 2021, 04:50:37 am »
You just couldn't do the math and give me a number?

Well, here is what I get on my end:

And my number is 1428ps.
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #584 on: September 25, 2021, 04:52:41 am »
Sorry, my number is 0.814ns or 814ps

By the way, I think I should use ck_180 instead of ck_270 to drive the command inputs.
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #585 on: September 25, 2021, 09:37:31 am »
Why test_ddr3_memory_controller.mem.main: at time 703390100.0 ps ERROR: Write Recovery =           5 is illegal @tCK(avg) = 2857.142578 ?

The relevant WRITE_RECOVERY coding could be found inside STATE_INIT_MRS_1

Note: 350MHz clock has  2.857142578ns period

« Last Edit: September 25, 2021, 09:42:39 am by promach »
 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #586 on: September 25, 2021, 09:56:54 am »
Write recovery is inside MRS0, not MRS1.
Yes, at 350MHz, a setting of 5 would be an error.
So, there is nothing wrong with the ddr3.v verilog model.  It is telling you the truth.
 
The following users thanked this post: promach

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #587 on: September 25, 2021, 11:34:38 am »
Quote
test_ddr3_memory_controller.mem.read_from_file: at time 703494385.0 ps ERROR: fseek to           x failed
$finish called at time : 703494385 ps : File "/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.srcs/sources_1/imports/DDR/ddr3.v" Line 665

Why fseek error for MPR read function during initial calibration process ?



Code: [Select]
restart
INFO: [Simtcl 6-17] Simulation restarted
run 710 us
test_ddr3_memory_controller.mem.file_io_open: at time                    0 WARNING: no +model_data option specified, using /tmp.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.0.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.1.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.2.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.3.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.4.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.5.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.6.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening /tmp/test_ddr3_memory_controller.mem.open_bank_file.7.
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 CAS Write Latency =           5
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 DLL Enable = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Output Drive Strength =          34 Ohm
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Additive Latency = 0
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Write Levelization = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Qoff = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Burst Length =  8
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Burst Order = Sequential
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 CAS Latency =           5
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Write Recovery =           6
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Power Down Mode = DLL on
test_ddr3_memory_controller.mem.cmd_task: at time 701958671.0 ps INFO: ZQ        long = 1
test_ddr3_memory_controller.mem.cmd_task: at time 701958671.0 ps INFO: Initialization Sequence is complete
test_ddr3_memory_controller.mem.cmd_task: at time 703430100.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703432957.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703435814.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703438671.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703441528.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 703481528.0 ps INFO: Read      bank 3 col 000, auto precharge 0
test_ddr3_memory_controller.mem.read_from_file: at time 703494385.0 ps ERROR: fseek to           x failed
$finish called at time : 703494385 ps : File "/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.srcs/sources_1/imports/DDR/ddr3.v" Line 665
run: Time (s): cpu = 00:00:24 ; elapsed = 00:01:39 . Memory (MB): peak = 7725.891 ; gain = 0.000 ; free physical = 1122 ; free virtual = 8664
« Last Edit: September 25, 2021, 11:37:33 am by promach »
 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #588 on: September 25, 2021, 11:38:37 am »
I don't know.
Could you possibly be reading an uninitialized or blank section of ram?
Maybe Xilinx cant do fseek?
Do the 'bank' files exist?
Does the simulator have system privileges to access the folder where the bank files exist?
« Last Edit: September 25, 2021, 11:40:39 am by BrianHG »
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #589 on: September 25, 2021, 11:53:37 am »
From googling, I found multiple usage of fseek with Xilinx, so I suppose this is not issue with Xilinx.

And I also have Initialization Sequence is complete from Micron simulation model log output.

What else could be wrong ?
 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #590 on: September 25, 2021, 12:00:30 pm »
Do the 'bank' files exist?
Does the simulator have system privileges to access the folder where the bank files exist?
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #591 on: September 25, 2021, 12:09:18 pm »
You are right, it is really some file permission issue which I had overlooked.

I have already done sudo chmod -R u+r ./* on /tmp and /home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/ directories, but why the read permission error dialog box keeps popping up ?

 

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 7199
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #592 on: September 25, 2021, 12:14:41 pm »
OS directory/file permissions is out of my league.

If I had the same error in Win7, I would have run Modelsim with Admin Privileges to circumvent the problem.  However, since Modelsim places the tmp folder on C:\tmp\ , there isn't a problem.

You will have to solve this problem on your own.
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #593 on: September 25, 2021, 12:19:09 pm »
ok, the culprit seems to be that the memory bank files are all empty ??  This is also why fopen() is okay but fseek() is not okay.

Code: [Select]
[phung@archlinux DDR]$ ls -hal /tmp/test_ddr3_memory_controller*
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.0
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.1
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.2
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.3
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.4
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.5
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.6
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.7
-rw-r--r-- 1 phung users 122M Sep 25 20:14 /tmp/test_ddr3_memory_controller_be_3477_1632569013.xilwvdat
[phung@archlinux DDR]$
« Last Edit: September 25, 2021, 12:35:40 pm by promach »
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #594 on: September 25, 2021, 03:35:20 pm »
I tried to set the xsim.simulate.xsim.more_options to -testplusarg model_data+./ , but the read permission error dialog box still keeps popping up.
 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #595 on: September 26, 2021, 10:04:29 am »
I suspect that those red X for DQS signals are due to ODDR2 primitives had not been migrated for Vivado environment, hence resulting in the incoming READ DQS that corresponds to the first READ preamble bit conflicting with the WRITE DQS.

May I know should I use OPPOSITE_EDGE mode or SAME_EDGE mode for ODDR primitive inside Vivado in this case?

 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #596 on: September 26, 2021, 11:13:47 am »
I got around the fseek error, it seems to be related to conflicting DQS from READ and WRITE operation.

Now, I have tCCD timing violation.  Any idea ?



Code: [Select]
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 7797.934 ; gain = 0.000 ; free physical = 891 ; free virtual = 7223
restart
INFO: [Simtcl 6-17] Simulation restarted
run 710 us
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.0.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.1.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.2.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.3.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.4.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.5.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.6.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.7.
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 CAS Write Latency =           5
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 DLL Enable = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Output Drive Strength =          34 Ohm
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Additive Latency = 0
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Write Levelization = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Qoff = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Burst Length =  8
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Burst Order = Sequential
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 CAS Latency =           5
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Write Recovery =           6
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Power Down Mode = DLL on
test_ddr3_memory_controller.mem.cmd_task: at time 701958671.0 ps INFO: ZQ        long = 1
test_ddr3_memory_controller.mem.cmd_task: at time 701958671.0 ps INFO: Initialization Sequence is complete
test_ddr3_memory_controller.mem.cmd_task: at time 703430100.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703432957.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703435814.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703438671.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703441528.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 703504385.0 ps INFO: Read      bank 3 col 000, auto precharge 1
test_ddr3_memory_controller.mem.chk_err: at time 703507242.0 ps ERROR:  tCCD violation during Read      to bank 3
test_ddr3_memory_controller.mem.cmd_task: at time 703507242.0 ps ERROR: Read      Failure.  Illegal burst interruption.
$stop called at time : 703507242 ps
run: Time (s): cpu = 00:00:18 ; elapsed = 00:01:37 . Memory (MB): peak = 7797.934 ; gain = 0.000 ; free physical = 430 ; free virtual = 7227
« Last Edit: September 26, 2021, 11:16:31 am by promach »
 

Offline SMB784

  • Frequent Contributor
  • **
  • Posts: 419
  • Country: us
    • Tequity Surplus
Re: DDR3 initialization sequence issue
« Reply #597 on: September 26, 2021, 12:26:57 pm »
ok, the culprit seems to be that the memory bank files are all empty ??  This is also why fopen() is okay but fseek() is not okay.

Code: [Select]
[phung@archlinux DDR]$ ls -hal /tmp/test_ddr3_memory_controller*
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.0
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.1
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.2
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.3
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.4
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.5
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.6
-rw-r--r-- 1 phung users    0 Sep 25 20:04 /tmp/test_ddr3_memory_controller.mem.open_bank_file.7
-rw-r--r-- 1 phung users 122M Sep 25 20:14 /tmp/test_ddr3_memory_controller_be_3477_1632569013.xilwvdat
[phung@archlinux DDR]$

Vivado hates most $f system task commands and won't work with many of them. There is a list of $f commands it works with on page 232 of UG901 (see attached screenshot). It's a very small list, which really limits what you can accomplish. I learned this the hard way when trying to parametrize $readmem tasks for multiple predefined RAM files.
« Last Edit: September 26, 2021, 12:29:51 pm by SMB784 »
 
The following users thanked this post: promach

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #598 on: September 26, 2021, 03:48:22 pm »
I have solved the tCCD timing violation, but both the fseek error and conflicting DQS issues come back again.

 

Offline promach

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #599 on: September 29, 2021, 11:52:57 am »
Why ldqs signal became X when only 4.5 cycles of ck_obuf clock signal had passed ?

 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf