Author Topic: DDR3 initialization sequence issue  (Read 49112 times)

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Online NorthGuy

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Re: DDR3 initialization sequence issue
« Reply #600 on: September 29, 2021, 01:46:13 pm »
Why ldqs signal became X when only 4.5 cycles of ck_obuf clock signal had passed ?

That is correct. When you issue a read command you get a burst of 8 bits - 8 edges of DQS.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #601 on: September 29, 2021, 02:31:00 pm »
My CL setting is only 5, so why 8 edges of DQS ?

 

Online NorthGuy

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Re: DDR3 initialization sequence issue
« Reply #602 on: September 29, 2021, 10:18:28 pm »
My CL setting is only 5, so why 8 edges of DQS ?

CL determines the latency between the read command an the first edge of DQS. Then you get 8 DQS edges (or 4 if you read half-burst) after which DQS gets released by the DDR3 chip and gets pulled to VDD/2.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #603 on: September 30, 2021, 08:34:04 am »
Wait, CL setting is computed with respect to posedge of ck signal ?

And why there is X at the end of my simulation waveform ?
 

Online NorthGuy

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Re: DDR3 initialization sequence issue
« Reply #604 on: September 30, 2021, 01:43:58 pm »
Wait, CL setting is computed with respect to posedge of ck signal ?

The read command is read by the DDR3 chip at pos edge, then, after the specified number of clocks, the chip produces the first DQS edge (which coincides with the clock edge pos edge). You will receive it later because of the round-trip delay. Your simulation is behavioural, so it probably doesn't model this delay.

And why there is X at the end of my simulation waveform ?

Because the transmission is over. Physically, both DQS and #DQS go to VDD/2. From the simulation viewpoint, the signal is undefined.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #605 on: September 30, 2021, 02:11:15 pm »
The FIRST piece of read data from MPR_READ_function had not even been transferred yet.

Code: [Select]
start_gui
open_project /home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.xpr
open_project /home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2021.1/data/ip'.
INFO: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'test_ddr3_memory_controller'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/opt/Xilinx/Vivado/2021.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/opt/Xilinx/Vivado/2021.1/data/xsim/xsim.ini' copied to run dir:'/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'test_ddr3_memory_controller' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.sim/sim_1/behav/xsim'
xvlog --incr --relax -L uvm -prj test_ddr3_memory_controller_vlog.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.sim/sim_1/behav/xsim'
xelab -wto 05448333b6914b52aac1122a43e7e957 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot test_ddr3_memory_controller_behav xil_defaultlib.test_ddr3_memory_controller xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2021.1
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2021.1/bin/unwrapped/lnx64.o/xelab -wto 05448333b6914b52aac1122a43e7e957 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot test_ddr3_memory_controller_behav xil_defaultlib.test_ddr3_memory_controller xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'tdqs_n' [/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.srcs/sources_1/imports/DDR/test_ddr3_memory_controller.v:662]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "test_ddr3_memory_controller_behav -key {Behavioral:sim_1:Functional:test_ddr3_memory_controller} -tclbatch {test_ddr3_memory_controller.tcl} -view {/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/test_ddr3_memory_controller_behav.wcfg} -log {simulate.log} -testplusarg model_data+./."
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config /home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/test_ddr3_memory_controller_behav.wcfg
source test_ddr3_memory_controller.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.0.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.1.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.2.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.3.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.4.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.5.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.6.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.7.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'test_ddr3_memory_controller_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 7602.480 ; gain = 46.828 ; free physical = 164 ; free virtual = 7649
restart
INFO: [Simtcl 6-17] Simulation restarted
run 710 us
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.0.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.1.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.2.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.3.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.4.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.5.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.6.
test_ddr3_memory_controller.mem.open_bank_file: at time 0 INFO: opening ././test_ddr3_memory_controller.mem.open_bank_file.7.
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 CAS Write Latency =           5
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
test_ddr3_memory_controller.mem.cmd_task: at time 701878671.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
test_ddr3_memory_controller.mem.cmd_task: at time 701892957.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 DLL Enable = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Output Drive Strength =          34 Ohm
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 ODT Rtt = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Additive Latency = 0
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Write Levelization = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
test_ddr3_memory_controller.mem.cmd_task: at time 701907242.0 ps INFO: Load Mode 1 Qoff = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Burst Length =  8
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Burst Order = Sequential
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 CAS Latency =           5
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Write Recovery =           6
test_ddr3_memory_controller.mem.cmd_task: at time 701921528.0 ps INFO: Load Mode 0 Power Down Mode = DLL on
test_ddr3_memory_controller.mem.cmd_task: at time 701958671.0 ps INFO: ZQ        long = 1
test_ddr3_memory_controller.mem.cmd_task: at time 701958671.0 ps INFO: Initialization Sequence is complete
test_ddr3_memory_controller.mem.cmd_task: at time 703430100.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703432957.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703435814.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703438671.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703441528.0 ps INFO: Precharge All
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
test_ddr3_memory_controller.mem.cmd_task: at time 703444385.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
test_ddr3_memory_controller.mem.cmd_task: at time 703501528.0 ps INFO: Read      bank 3 col 000, auto precharge 1
test_ddr3_memory_controller.mem.read_from_file: at time 703514385.0 ps ERROR: fseek to           x failed
$finish called at time : 703514385 ps : File "/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.srcs/sources_1/imports/DDR/ddr3.v" Line 665
run: Time (s): cpu = 00:00:19 ; elapsed = 00:01:44 . Memory (MB): peak = 7611.617 ; gain = 7.004 ; free physical = 158 ; free virtual = 7637
« Last Edit: September 30, 2021, 02:14:11 pm by promach »
 

Online NorthGuy

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Re: DDR3 initialization sequence issue
« Reply #606 on: September 30, 2021, 02:27:34 pm »
The FIRST piece of read data from MPR_READ_function had not even been transferred yet.

You see pulses on DQS meaning the DDR3 chip is transmitting something.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #607 on: September 30, 2021, 02:42:00 pm »
I think the root cause for X on DQS is still because of conflicting write DQS and read DQS, hence the fseek error.

Let me check my ODDR primitive for DQS.
 

Offline SMB784

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Re: DDR3 initialization sequence issue
« Reply #608 on: September 30, 2021, 03:10:39 pm »
I think the root cause for X on DQS is still because of conflicting write DQS and read DQS, hence the fseek error.

Let me check my ODDR primitive for DQS.

Are you sure $fseek is a valid command in vivado?  I don't see it listed in UG901, which usually means it doesn't work.  The only ones that are guaranteed to work are the ones listed as supported in UG901

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #609 on: October 01, 2021, 01:12:57 am »
I think the root cause for X on DQS is still because of conflicting write DQS and read DQS, hence the fseek error.

Let me check my ODDR primitive for DQS.

Are you sure $fseek is a valid command in vivado?  I don't see it listed in UG901, which usually means it doesn't work.  The only ones that are guaranteed to work are the ones listed as supported in UG901

LOL, if the command isn't know, then how would vivado know that $fseek is a command which seeks to a position?

Code: [Select]
test_ddr3_memory_controller.mem.read_from_file: at time 703514385.0 ps ERROR: fseek to           x failed
Wouldn't is say it is an unsupported or unknown command?
 
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Offline SMB784

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Re: DDR3 initialization sequence issue
« Reply #610 on: October 01, 2021, 06:06:29 pm »
I think the root cause for X on DQS is still because of conflicting write DQS and read DQS, hence the fseek error.

Let me check my ODDR primitive for DQS.

Are you sure $fseek is a valid command in vivado?  I don't see it listed in UG901, which usually means it doesn't work.  The only ones that are guaranteed to work are the ones listed as supported in UG901

LOL, if the command isn't know, then how would vivado know that $fseek is a command which seeks to a position?

Code: [Select]
test_ddr3_memory_controller.mem.read_from_file: at time 703514385.0 ps ERROR: fseek to           x failed
Wouldn't is say it is an unsupported or unknown command?

You would be surprised at how little Vivado will tell you when something is wrong.  I only bring up the issue because I tried various ways to manipulate memory modules and many of them failed due to vivado not recognizing a certain $f command without providing any error or warning messages.

That said, its possible that $fseek is perfectly ok, but it would be wise to check it in vivado to make sure it does indeed work, given that it isn't explicitly listed in UG901 as a supported command

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #611 on: October 02, 2021, 04:32:24 am »
The fseek error happen alongside with the read permission error

Note: I already tried setting absolute path for the following simulation property/parameter

Code: [Select]
set_property -name {xsim.simulate.xsim.more_options} -value {-testplusarg model_data+/home/phung/Downloads/DDR_backup/DDR_Xilinx_Vivado/DDR_Xilinx_Vivado.sim/sim_1/behav/xsim} -objects [get_filesets sim_1]

INFO: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.

Besides, the fseek error does not seem to be related to DQS as shown below.  I previously suspected that conflicting DQS might be the reason for the fseek error.

Could anyone advise ?

« Last Edit: October 02, 2021, 08:20:41 am by promach »
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #612 on: October 02, 2021, 11:39:25 am »
I managed to eliminate all conflicting DQS/DQ issues.

As you can see in the second picture below, $fseek() is recognized as a valid command, changing the naming of the command will rendered it undetected by Vivado code pre-processing highlight interpreter.

So, all I could say is that Vivado might had done something strange when it comes to reading file content during fseek() operation.

Please correct me if wrong.





 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #613 on: October 08, 2021, 03:34:34 pm »
@BrianHG

As for the fseek() issue, I think I will try to migrate the work to test inside Quartus while I try to check what is wrong inside Xilinx Vivado.

I noticed that there are 3 different types of PLL IP core inside Quartus IP Catalog.
May I know which IP core should I use for dynamic phase shift on the incoming READ DQS strobe signal ?

Which special parameters inside the PLL IP core should I pay attention to in this case ?
« Last Edit: October 08, 2021, 03:50:45 pm by promach »
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #614 on: October 08, 2021, 04:33:51 pm »
Older Cyclone, MAX5/MAX10, Stratix I/II/II and Arria I/II/III PLL:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/75a3d5fe0ef248d7826fdf5fab9c369686c6aa2f/BrianHG_DDR3/BrianHG_DDR3_PLL.sv#L305

Newer Cyclone V, Arria V and Stratix V PLL: (Note that these FPGA PLLs also contain support for multiple PLL chaining and precision DLL blocks which I am not using.)
https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/75a3d5fe0ef248d7826fdf5fab9c369686c6aa2f/BrianHG_DDR3/BrianHG_DDR3_PLL.sv#L472
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #615 on: October 08, 2021, 04:49:07 pm »
You are using BOTH altpll and altera_pll ?
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #616 on: October 08, 2021, 05:31:08 pm »
You are using BOTH altpll and altera_pll ?

I'm using 1 type of PLL at a time.  It depends on which FPGA type you choose to build my project for.
Both are in my code and one is auto-selected based on parameter string 'FPGA_FAMILY'.

You may read altera data sheets on both.
Altera also has a megafunction wizard which will auto-setup the PLL for you and generate a .v code example.
 
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Offline promach

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Re: DDR3 initialization sequence issue
« Reply #617 on: October 09, 2021, 03:01:27 am »
Quote
I'm using 1 type of PLL at a time.  It depends on which FPGA type you choose to build my project for.
Both are in my code and one is auto-selected based on parameter string 'FPGA_FAMILY'.

You may read altera data sheets on both.

Where did you exactly find altera_pll IP core inside IP catalog ?
And why are you not using ALTPLL_RECONFIG ?




Quote
Altera also has a megafunction wizard which will auto-setup the PLL for you and generate a .v code example.

You mean the following ALTCLKCTRL megafunction wizard ?

 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #618 on: October 09, 2021, 04:26:45 am »
No, that one is for making a PLL which you can in-system reconfigure.
You only need the ALTPLL which is the one I'm using.
 
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Offline promach

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Re: DDR3 initialization sequence issue
« Reply #619 on: October 10, 2021, 02:53:24 am »
For Xilinx Vivado fseek() issue, I think I have found the root cause, but I have no feasible workaround so far.

There is 0.1ns difference between ck_n_obuf (which is connected directly to DDR3 RAM) and ck_180 (which drives the FPGA DDR3 RAM controller logic)

« Last Edit: October 10, 2021, 03:26:03 am by promach »
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #620 on: October 15, 2021, 03:00:10 pm »
There is no option for dynamic phase shift ?

 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #621 on: October 15, 2021, 06:32:05 pm »
You already have it enabled, see the inputs in the diagram...

You can phase shift every clock output individually with the phasecounterselect input.

Read the documentation.

The phasecounterselect doesn't exactly match the c# core number output with altpll since there is an address which allows you to adjust the internal global phase as well as the feedback phase if I remember correctly.

The clock phase shift setting you see on every c# core page is what each core output will default to after power-up or a PLL reset.
 

Offline promach

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Re: DDR3 initialization sequence issue
« Reply #622 on: October 16, 2021, 04:44:33 am »
Quote
The phasecounterselect doesn't exactly match the c# core number output with altpll since there is an address which allows you to adjust the internal global phase as well as the feedback phase if I remember correctly.

The clock phase shift setting you see on every c# core page is what each core output will default to after power-up or a PLL reset.

According to alt_pll user guide , why do the signals phasecounterselect[3..0], phaseupdown, phasestep need to be of tri0 or tri1 type ?

Besides, what do you exactly mean by internal global phase as well as the feedback phase ?

Code: [Select]
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll

// ============================================================
// File Name: pll_tuneable.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Standard Edition
// ************************************************************


//Copyright (C) 2020  Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors.  Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_tuneable (
areset,
inclk0,
pfdena,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
locked,
phasedone);

input   areset;
input   inclk0;
input   pfdena;
input [2:0]  phasecounterselect;
input   phasestep;
input   phaseupdown;
input   scanclk;
output   c0;
output   c1;
output   locked;
output   phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0   areset;
tri1   pfdena;
tri0 [2:0]  phasecounterselect;
tri0   phasestep;
tri0   phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

wire [4:0] sub_wire0;
wire  sub_wire3;
wire  sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire  c0 = sub_wire1;
wire  c1 = sub_wire2;
wire  locked = sub_wire3;
wire  phasedone = sub_wire4;
wire  sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};

altpll altpll_component (
.areset (areset),
.inclk (sub_wire6),
.pfdena (pfdena),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.phaseupdown (phaseupdown),
.scanclk (scanclk),
.clk (sub_wire0),
.locked (sub_wire3),
.phasedone (sub_wire4),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 8,
altpll_component.clk1_phase_shift = "1250",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_tuneable",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_USED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 1,
altpll_component.width_clock = 5,
altpll_component.width_phasecounterselect = 3;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "400.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "400.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "1.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_tuneable.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "1250"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: pfdena 0 0 0 0 INPUT VCC "pfdena"
// Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @pfdena 0 0 0 0 pfdena 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 3 0 phasecounterselect 0 0 3 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_tuneable.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_tuneable.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_tuneable.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_tuneable.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_tuneable.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_tuneable_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_tuneable_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
« Last Edit: October 16, 2021, 12:43:36 pm by promach »
 

Offline promach

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  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #623 on: October 16, 2021, 04:03:29 pm »
Why is Quartus giving the following error relating to i_user_data_address and write_enable signals alone ?

Note: Both Vivado and ISE tools do not have any error during synthesis process.

Code: [Select]
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[16]" at test_ddr3_memory_controller.v(351)
Error (10029): Constant driver at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[15]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[14]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[13]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[12]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[11]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[10]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[9]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[8]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[7]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[6]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[5]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[4]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[3]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[2]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[1]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "i_user_data_address[0]" at test_ddr3_memory_controller.v(351)
Error (10028): Can't resolve multiple constant drivers for net "write_enable" at test_ddr3_memory_controller.v(351)
Error (12153): Can't elaborate top-level user hierarchy
 

Online BrianHG

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Re: DDR3 initialization sequence issue
« Reply #624 on: October 16, 2021, 06:18:08 pm »
It means in 2 or more different locations your code, you made 'i_user_data_address' = to 1 value, then another.

Or you made an = assignment and also somewhere else in logic a <= to the reg 'i_user_data_address'.

Or, you are making i_user_data_address <= to a value and have it also tied to a sub-module's .xxx(i_user_data_address) who is set to an output, ie that module is setting i_user_data_address to a value while in you top modules main code, you are also making it <= to a value as well.  IE, 2 drivers to the same reg.

Last case may have to do with making the reg <= a value in 1 clock domain while simultaneously making it <= to another value in another clock domain.
« Last Edit: October 16, 2021, 06:34:18 pm by BrianHG »
 
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