Electronics > FPGA

DDR3 initialization sequence issue

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BrianHG:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/archives/ug-m10-gpio-15.1.pdf

Read page 50.

BrianHG:
The end result of my parameter selection is a DDR buffer which functions identically to altera Cyclone's altddio_bidir buffer with the following settings:

https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/75a3d5fe0ef248d7826fdf5fab9c369686c6aa2f/BrianHG_DDR3/BrianHG_DDR3_IO_PORT_ALTERA.sv#L390

Now, the 1 piece of code I made will operate identically for Max10 and Cyclone V/IV/III.

promach:
I do not understand why you use .din( 2'b10 )

BrianHG:
Since it is a 1 bit DDR buffer, and that is the SDR input -to- DDR data output which will be fed out, a 0 will be sent when the DDR_CLK goes high, and a 1 will be sent when the DDR_CLK goes low.

promach:
What about inclock and outclock ?

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