Electronics > FPGA

DDR3 initialization sequence issue

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Why does a simple tri-state buffer require clock to gate the data signals ?  I suppose it is the job of OE (output enable) signal to do this ?

As for the fseek() issue, it seems that row = row_pipeline[0]; contains the XXX value.
But I am not sure what causes this.

Note: According to the simulation waveform, there is no XXX value in any of the DDR command inputs signals

I have gotten around the fseek() issue by exporting Vivado simulation libraries to Modelsim.  It seems that it is due to Vivado internal issue, not related to any of the user application coding.

Modelsim waveform using SOFTWARE PLL approach

Modelsim waveform using HARDWARE PLL approach

What causes the col address to follow this order : 5, 6, 7, 4, 1, 2, 3, 0 ?

For this vcd file, why is the DRAM read operation (709746ns) not reading back the DQ values written at the same address (4096) during DRAM write operation (709578ns) ?

read and write latency = five ck cycles


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