Just so we are clear, the absolute bottom section of my sim, the nodes under 'DDR3_PHY DataPath' is not what I'm transmitting to the actual DQS/DQ IO pins just above. Those nodes are Altera's DDR input buffer reading the IO pins values above and separating it into the low and high 2x wide, 1/2 speed path. The values I send into Altera's DDR output pin driver are hidden/not visible in my sim screenshot. However, it is actually what you see coming out, flipped upside-down, 2 CKs earlier with the 90 degree shift.
Now as for the 'Don't Care' in the datasheet. Ok, Ok, Ok... Another lesson in I can't believe I'm saying this:
Looking at the datasheet and seeing 'Don't Care' is not permission to generate sloppy loose code and ugly waveforms. It is there for a reason. The DDR3 allows you to share / interleave multiple (not just 2, but even 4 or more) DDR3 rams on the exact same buss. This is why you have a CS# and it should only go low for the 1 clock you issue a command as multiple CS# coming out of your FPGA would each go to a different DDR3 chip to allow individual commanding of each chip sharing every single other wire/IO. The 'Don't Care' positions is the free area where you can control the other ram chips as you plan their commands so the their data buss access each fit in that spare space. This means your code should be sharp and fit everything in it's place where it belongs exactly as what's in the datasheet, do not bleed into the 'Don't Care' zones.
Ok, it looks as if you have enough understanding of how to use the Sim & DDR3 model as well as debug it's given violations to you. I have some finishing cleanup touches on work I'm doing here as I want to publish my public domain code within a few days.