Author Topic: DDR3 initialization sequence issue  (Read 62296 times)

0 Members and 1 Guest are viewing this topic.

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #75 on: June 02, 2021, 02:03:22 pm »
@asmi  in the previous post, I am trying to find out why when ldq_w and udq_w are carrying value of 2, 4 or 6, dq carry a value of 0 ?
Why don't you find out first why your DQS starts immediately with the command, as opposed to when it should (after write latency - 1 cycle)?

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #76 on: June 02, 2021, 02:22:04 pm »
@asmi I understand your concern about DQS preamble bit, however look carefully in the timing diagram by Micron, it is marked as DONT_CARE.

But let me try yoru suggestion to maybe get around the tRP violation for WRAP command.

However, this had nothing to with why DQ carries value of 0 when ldq_w is not carrying value of 0
 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #77 on: June 02, 2021, 03:34:09 pm »
Code: [Select]
`ifdef USE_x16
wire [(DQ_BITWIDTH >> 1)-1:0] ldq_w = data_to_ram;  // input data stream of 'data_to_ram' is NOT serialized
wire [(DQ_BITWIDTH >> 1)-1:0] udq_w = data_to_ram;  // input data stream of 'data_to_ram' is NOT serialized
assign dq_w = {udq_w, ldq_w};
`else
assign dq_w = data_to_ram;  // input data stream of 'data_to_ram' is NOT serialized
`endif
your ldq_w and udp_w are both referring to first 8 bits of data_to_ram vector.

Also why your dqs'es are so wide?
wire [DQS_BITWIDTH-1:0] dqs = {udqs, ldqs};
wire [DQS_BITWIDTH-1:0] dqs_n = {udqs_n, ldqs_n};

They are supposed to be 1 bit per byte, or 2 in case of x16 DDR3 memory you seem to be using.

Your code is extremely hard to read due to a ton of conditional directives, so it's hard to tell if a piece of code is actually used or not.

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #78 on: June 02, 2021, 03:39:52 pm »
@asmi  DQS_BITWIDTH and DQ_BITWIDTH are two different parameter.  Look carefully
 

Offline asmi

  • Super Contributor
  • ***
  • Posts: 2728
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #79 on: June 02, 2021, 04:01:35 pm »
@asmi  DQS_BITWIDTH and DQ_BITWIDTH are two different parameter.  Look carefully
My first comment about dq still stands. Both ldq and udq are assigned the same values, I don't know if it's intentional, but something tells me it's not.
Also please show us the waveform that is coming into the actual memory, as opposed to what comes out of your controller. These two are not necessarily the same.

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #80 on: June 02, 2021, 04:47:20 pm »
Just so we are clear, the absolute bottom section of my sim, the nodes under 'DDR3_PHY DataPath' is not what I'm transmitting to the actual DQS/DQ IO pins just above.  Those nodes are Altera's DDR input buffer reading the IO pins values above and separating it into the low and high 2x wide, 1/2 speed path.  The values I send into Altera's DDR output pin driver are hidden/not visible in my sim screenshot.  However, it is actually what you see coming out, flipped upside-down, 2 CKs earlier with the 90 degree shift.

Now as for the 'Don't Care' in the datasheet.  Ok, Ok, Ok...  Another lesson in I can't believe I'm saying this:

Looking at the datasheet and seeing 'Don't Care' is not permission to generate sloppy loose code and ugly waveforms.  It is there for a reason.  The DDR3 allows you to share / interleave multiple (not just 2, but even 4 or more) DDR3 rams on the exact same buss.  This is why you have a CS# and it should only go low for the 1 clock you issue a command as multiple CS# coming out of your FPGA would each go to a different DDR3 chip to allow individual commanding of each chip sharing every single other wire/IO.  The 'Don't Care' positions is the free area where you can control the other ram chips as you plan their commands so the their data buss access each fit in that spare space.  This means your code should be sharp and fit everything in it's place where it belongs exactly as what's in the datasheet, do not bleed into the 'Don't Care' zones.

Ok, it looks as if you have enough understanding of how to use the Sim & DDR3 model as well as debug it's given violations to you.  I have some finishing cleanup touches on work I'm doing here as I want to publish my public domain code within a few days.
« Last Edit: June 02, 2021, 05:05:30 pm by BrianHG »
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #81 on: June 04, 2021, 11:57:05 am »
From the modelsim console log, it seems that the data loopback(readback) works.

However, how to simulate "inout" dqs signals correctly inside modelsim ?
Note: I tried changing 1'b0 to 1'bz  , but it does not help.

 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #82 on: June 04, 2021, 09:52:49 pm »
For tristate, you need to assign a 'z' for every wire in the bus.
1'bz  will only make 1 wire, bit io_pins[0:0] in the bus tristate, while the rest, io_pins[bus_size-1:1] will be undefined. IE 'x'  IO error conflicts on a shared tristate bus I believe are an 'X'.  Read the modelsim manual about the waveform legend and what symbols mean what.

Properly done non-conflicting tristate in modelsim should show a 'BLUE' trace in the middle and when you place the cursor on it, it should read 'zzzzzzzzzzz'...

« Last Edit: June 04, 2021, 09:59:13 pm by BrianHG »
 
The following users thanked this post: promach

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #83 on: June 05, 2021, 02:06:55 am »
I tried your suggestion and there are no more XXXX for dqs, but why Micron DDR3 simulation model does not assert the dqs signals during RDAP command ?

https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L847

 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #84 on: June 05, 2021, 02:39:38 am »
Code: [Select]
assign dqs = {udqs, ldqs};
assign dqs_n = {udqs_n, ldqs_n};
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #85 on: June 05, 2021, 02:58:58 am »
Yes, but in your sim, you need to show the 'PINS' in between you DDR3 controller and Micron's ram Model.

Mine seems to work, see:
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #86 on: June 05, 2021, 03:16:49 am »
Here you go:

 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #87 on: June 05, 2021, 03:39:46 am »
What do the pin definitions look like in your test-bench top?

Are they an 'inout'?

This is my TB:
Code: [Select]
// ********** Results from DDR3_PHY_SEQ.
inout  logic                       DDR3_RESET_n;  // DDR3 RESET# input pin.
inout  logic [DDR3_NUM_CK-1:0]     DDR3_CK_p;     // DDR3_CK ****************** YOU MUST SET THIS IO TO A DIFFERENTIAL LVDS or LVDS_E_3R
inout  logic [DDR3_NUM_CK-1:0]     DDR3_CK_n;     // DDR3_CK ****************** YOU MUST SET THIS IO TO A DIFFERENTIAL LVDS or LVDS_E_3R
                                                  // ************************** port to generate the negative DDR3_CK# output.
                                                  // ************************** Generate an additional DDR_CK_p pair for every DDR3 ram chip.

inout  logic                       DDR3_CKE;      // DDR3 CKE

inout  logic                       DDR3_CS_n;     // DDR3 CS#
inout  logic                       DDR3_RAS_n;    // DDR3 RAS#
inout  logic                       DDR3_CAS_n;    // DDR3 CAS#
inout  logic                       DDR3_WE_n;     // DDR3 WE#
inout  logic                       DDR3_ODT;      // DDR3 ODT

inout  logic [DDR3_WIDTH_ADDR-1:0] DDR3_A;        // DDR3 multiplexed address input bus
inout  logic [DDR3_WIDTH_BANK-1:0] DDR3_BA;       // DDR3 Bank select
inout  logic [DDR3_WIDTH_DM-1  :0] DDR3_DM;       // DDR3 Write data mask. DDR3_DM[0] drives write DQ[7:0], DDR3_DM[1] drives write DQ[15:8]...
                                                  // ***on x8 devices, the TDQS is not used and should be connected to GND or an IO set to GND.

inout  logic [DDR3_WIDTH_DQ-1:0]   DDR3_DQ;       // DDR3 DQ data IO bus.
inout  logic [DDR3_WIDTH_DQS-1:0]  DDR3_DQS_p;    // DDR3 DQS ********* IOs. DQS[0] drives DQ[7:0], DQS[1] drives DQ[15:8], DQS[2] drives DQ[23:16]...
inout  logic [DDR3_WIDTH_DQS-1:0]  DDR3_DQS_n;    // DDR3 DQS ********* IOs. DQS[0] drives DQ[7:0], DQS[1] drives DQ[15:8], DQS[2] drives DQ[23:16]...
                                                  // ****************** YOU MUST SET THIS IO TO A DIFFERENTIAL LVDS or LVDS_E_3R
                                                  // ****************** port to generate the negative DDR3_DQS# IO.

 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #88 on: June 05, 2021, 03:48:44 am »
See https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L184-L187

Code: [Select]
inout ldqs, // lower byte data strobe
inout ldqs_n,
inout udqs, // upper byte data strobe
inout udqs_n
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #89 on: June 05, 2021, 04:01:27 am »
That's your controller.  What about your testbench source and it's wiring to Mircon's ddr3.v?
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #90 on: June 05, 2021, 04:04:11 am »
I had also done the same for testbench, see https://github.com/promach/DDR/blob/main/test_ddr3_memory_controller.v#L125-L128 which I had also already used inout for the dqs signals

So, something else is wrong, maybe with the mode registers settings ?
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #91 on: June 05, 2021, 04:16:11 am »
I don't know.  It should work.  It seems to be outputting data.  I usually see both coming up together with a preamble on the DQS.
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #92 on: June 05, 2021, 05:59:39 am »
Ok, the following waveform shows that Micron DDR3 simulation model outpus the dqs signals correctly.

So, this line of coding https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L845-L847 for udqs is still wrong

Code: [Select]
assign udqs = ((main_state == STATE_WRITE) || (main_state == STATE_WRITE_AP) ||
   (main_state == STATE_WRITE_DATA)) ?
udqs_w : {(DQS_BITWIDTH >> 1){1'bz}};  // dqs value of 1'bz is for input

« Last Edit: June 05, 2021, 06:08:45 am by promach »
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #93 on: June 05, 2021, 06:38:37 am »
Query in the sim the value of DQS_BITWIDTH .
Why are you dividing it by 2?
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #94 on: June 05, 2021, 06:45:32 am »
you mean   (DQS_BITWIDTH >> 1)    ?

Because of https://github.com/promach/DDR/blob/main/test_ddr3_memory_controller.v#L191

dqs consists of udqs and ldqs
« Last Edit: June 05, 2021, 06:50:26 am by promach »
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #95 on: June 05, 2021, 07:56:39 am »
I tried changing to the following, but still does not change anything.

Code: [Select]
wire [DQS_BITWIDTH-1:0] dqs
= ((main_state == STATE_WRITE) || (main_state == STATE_WRITE_AP) ||
       (main_state == STATE_WRITE_DATA)) ?
{udqs, ldqs} : {DQS_BITWIDTH{1'bz}};  // dqs value of 1'bz is for input

wire [DQS_BITWIDTH-1:0] dqs_n
= ((main_state == STATE_WRITE) || (main_state == STATE_WRITE_AP) ||
       (main_state == STATE_WRITE_DATA)) ?
{udqs_n, ldqs_n} : {DQS_BITWIDTH{1'bz}};  // dqs value of 1'bz is for input
 

Online BrianHG

  • Super Contributor
  • ***
  • Posts: 7638
  • Country: ca
Re: DDR3 initialization sequence issue
« Reply #96 on: June 05, 2021, 09:00:21 am »
But you need to read the data from the wires DQS & DQS_n, not ldqs/udqs.  Those are buried before the INOUT port.
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #97 on: June 05, 2021, 09:05:28 am »
So, how should I modify https://github.com/promach/DDR/blob/main/test_ddr3_memory_controller.v#L191 ?

Code: [Select]
wire [DQS_BITWIDTH-1:0] dqs = {udqs, ldqs};
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
 

Offline promachTopic starter

  • Frequent Contributor
  • **
  • Posts: 875
  • Country: us
Re: DDR3 initialization sequence issue
« Reply #99 on: June 07, 2021, 09:06:41 am »
I have finished simulating the Micron DDR3 controller,

the DDR3 schematics and verilog code are located at https://github.com/promach/DDR

However, I have concern on implementing it on the Spartan-6_XC6SLX16_FTG256 FPGA.

Besides ODDR2 primitive , what other primitives do I need in this case ?
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf