DDR3 initialization sequence issue

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promach:
Could anyone point out if there are issues with this DDR3 initialization sequence ?

Note: The DDR3 RAM memory controller is not working yet so far.

BrianHG:
Simulate your code driving Mircron's DDR3 Verilog Model. It will tell you every success and violation for every DDR3 command you send.

A successful powerup should look something like this:

--- Code: ---# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.0.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.1.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.2.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.3.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.4.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.5.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.6.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file: at time 0 INFO: opening /tmp/BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.open_bank_file.7.
# ** Error (suppressible): (vsim-8630) Infinity results from division operation.
# Time: 0 ps Iteration: 0 Process: /BrianHG_DDR3_PHY_SEQ_tb/sdramddr3_0/#ASSIGN#542 File: ddr3.v Line: 542
# ** Error (suppressible): (vsim-8630) Infinity results from division operation.
# Time: 0 ps Iteration: 0 Process: /BrianHG_DDR3_PHY_SEQ_tb/sdramddr3_0/#ASSIGN#543 File: ddr3.v Line: 543
# ** Error (suppressible): (vsim-8630) Infinity results from division operation.
# Time: 0 ps Iteration: 0 Process: /BrianHG_DDR3_PHY_SEQ_tb/sdramddr3_0/#ASSIGN#544 File: ddr3.v Line: 544
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001913000.0 ps INFO: Load Mode 2
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001913000.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001913000.0 ps INFO: Load Mode 2 CAS Write Latency = 6
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001913000.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001913000.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001913000.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001921000.0 ps INFO: Load Mode 3
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001921000.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001921000.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1 DLL Enable = Enabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1 Additive Latency = 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1 Write Levelization = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001929000.0 ps INFO: Load Mode 1 Qoff = Enabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001937000.0 ps INFO: Load Mode 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001937000.0 ps INFO: Load Mode 0 Burst Length = 8
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001937000.0 ps INFO: Load Mode 0 Burst Order = Sequential
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001937000.0 ps INFO: Load Mode 0 CAS Latency = 7
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001937000.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001937000.0 ps INFO: Load Mode 0 Write Recovery = 8
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001937000.0 ps INFO: Load Mode 0 Power Down Mode = DLL on
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001961000.0 ps INFO: ZQ long = 1
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001961000.0 ps INFO: Initialization Sequence is complete
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1002993000.0 ps INFO: Load Mode 3
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1002993000.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1002993000.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003017000.0 ps INFO: Read bank 0 col 000, auto precharge 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003030000.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003031000.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003032000.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003033000.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003034000.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003035000.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003036000.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003037000.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003141000.0 ps INFO: Load Mode 3
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003141000.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003141000.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003253000.0 ps INFO: Activate bank 7 row 0004
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003267000.0 ps INFO: Write bank 7 col 000, auto precharge 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003275000.0 ps INFO: Write bank 7 col 010, auto precharge 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.main: at time 1003275000.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003280000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000000 data = eeff
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003281000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000001 data = ccdd
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003282000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000002 data = aabb
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003283000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000003 data = 8899
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003284000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000004 data = 6677
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003285000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000005 data = 4455
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003286000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000006 data = 2233
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003287000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000007 data = 0011
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003288000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000010 data = eeff
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003289000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000011 data = ccdd
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003290000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000012 data = aabb
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003291000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000013 data = 8899
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003292000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000014 data = 6677
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003293000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000015 data = 4455
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003294000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000016 data = 2233
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003295000.0 ps INFO: WRITE @ DQS= bank = 7 row = 0004 col = 00000017 data = 0011
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.main: at time 1003297000.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003303000.0 ps INFO: Read bank 7 col 000, auto precharge 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1003311000.0 ps INFO: Read bank 7 col 010, auto precharge 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.data_task: at time 1003316000.0 ps INFO: READ @ DQS= bank = 7 row = 0004 col = 00000000 data = eeff
.....

--- End code ---

The warnings & divide by zero at the top are just that I do not have a memory preset data files, IE the model powers up with the ram initialized to h'xxxx instead of fake data.

You need to get to line:

--- Code: ---# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 1001961000.0 ps INFO: Initialization Sequence is complete
--- End code ---

Without any errors. Also, all read and writes, activates and prechargs and refreshes should never produce an error, otherwise your DDR3 code has timing bugs, or, you have entered the wrong tCK figures from the data sheet. The writes actually place data in the simulated DDR3 ram model and the reads should return the data you have written.

promach:
However, my current verilog code does not yet support DLL on mode for which the Micron simulation model requires.

Do you have some other alternative method or I have to use Micron simulation model ?

Besides, the Micron simulation model is for HSpice software for which I do not have access with.

BrianHG:
For the sim, just turn on the DLL. Other than requiring a to spec clock (minimum 303MHz), the remainder of the functionality is identical.

promach:
I do not have access to HSpice software

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