You showed me a tIS violation.
You told me you were clocking Micron's 'ddr3.v' with your clk_serdes.
I'm trying to tell you you should have a proper generated DDR3_CK output from your design to feed Micron's 'ddr3.v' s CK input.
tIS is a setup timing relationship/clearance error between the CK and the command inputs.
If your FPGA's CK output is authentically true to clk_serdes as it is with all the command lines, then you have a tIS problem and it will also be a problem when you build an actual FPGA.
In fact, I know you have a tIS setup error visibly within you simulation waveform.
Now, there is a cheat to fix this, but, applying such a cheat is not proper form and it will come back to haunt you when you build an FPGA and you have not properly accommodated for a true CK output from the FPGA. Either properly generate your true CK output or use the cheat.
Maybe searching for some other vendor's app notes on FPGA DDR3 implementations might help you out. Lattice has some good info on how they generate their clocks, command, and latch data. They kind of sit in-between Altera's old method and Xilinx current implementation.