DDR3 initialization sequence issue

[promach]

All 'i_user_data_address' assignment logic are in the same always block.

And it is an input to the submodule.

I have commented out main_state inside the if-statement which might be the cause for clock domain conflict, but not helping.

[BrianHG]

Maybe it is 'clk_serdes' on line '351'.
How is 'clk_serdes' generated?

[promach]

'clk_serdes' is generated from ALT_PLL core.

Note: The github version is targeted at Xilinx platform, so you might need to turn on the ifdef ALTERA option manually for code debugging purpose.

[BrianHG]

Well, the ifdef in circuit will be ignored is not selected.

The modelsim which came with altera knows how to properly simulated altera IP like it's ALTPLL and DDRIO.  If you select CycloneIV as an FPGA, it can be setup to simulate with actual true IO timing.

Have you tried changing which default Verilog version Quartus uses?
In 'Assignment Settings / Compiler Settings / Verilog HDL Input', you may choose:
Verilog 1995
Verilog 2005
SystemVerilog

If this does work, it will not tell you what you have done which made your code not work with for example 'Verilog 1995'.  (Well maybe you will see a 'warning' in the system messages window during compile which might offer a better clue.)  It will be then up to you whether you want to further hunt down the issue.

Warning about Cyclone IV/V and Max10, they use different types of DDR ip and Quartus may compile Cyclone's DDR ip when generating a Max10 FPGA, but, it will not work on silicon and there is no warning.  I did complain on Intel's forum, but not much came of it.

[promach]

Modelsim will not launch unless Quartus had finished the synthesis process.

I am using systemverilog for the file type if that is what you are asking.

I am really stucked here with ISE tool not being able to simulate Micron simulation model in systemverilog, Vivado tool not being able to get past fseek() error, and Quartus tool with multiple driver synthesis error.

Let me also change the DDR IP as you had suggested for Max10 and see if this helps with the synthesis error.

[BrianHG]

Modelsim will not launch unless Quartus had finished the synthesis process.

I am using systemverilog for the file type if that is what you are asking.

I am really stucked here with ISE tool not being able to simulate Micron simulation model in systemverilog, Vivado tool not being able to get past fseek() error, and Quartus tool with multiple driver synthesis error.

Let me also change the DDR IP as you had suggested for Max10 and see if this helps with the synthesis error.

Yes, Altera modelsim will launch without Quartus, just click on it's icon.  You just need to know the setup commands and how to include project files in the transcript window.  In fact, I now go to Quartus last as working in Modelsim alone only takes around 1-2 seconds to completely re-compile a build.  The instructions are in my DDR3 build, in the simulation instructions on my setup_****.do and run_****.do script files.  They have the library includes for the altera IP on the 'vsim' line while the vlog's I use to include my project source files.  If you want full timing simulations, yes it must first completely compile for a FPGA in Quartus.

[promach]

Ok, it seems that the multiple driver synthesis error might be originating from the generate for loop

[promach]

I have solved the multiple driver synthesis error in Quartus.

May I know where I could find tri-state buffer primitive for Altera MAX10 ?

I tried to search for keyword "buf" inside the IP catalog, but nothing came up.

[BrianHG]

Functions to look at in attached images.
The Max10 has everything squished into their GPIO.
Run the wizard and let it generate sample verilog code for you.

[BrianHG]

As for a simple tristate anywhere, there is always:

inout  iopin,

reg iopin_oe;
reg iopin_outdata;
assign iopin = iopin_oe ? iopin_outdata : 1'bz ;

...
readback_iopin <= iopin ;

[promach]

I tried to search for more information about MAX 10 GPIO , but there is not much info about tri-state buffer ?

[BrianHG]

The tristate is an input to the GPIO.
Run the megawizard and read and look at the example generated verilog code.
ok just use the verilog code example 2 posts up.

[promach]

the simple verilog code example is not enough for double-data-rate purpose.

Anything wrong with the following setting for DQS tri-state buffer ?

[BrianHG]

the simple verilog code example is not enough for double-data-rate purpose.

Anything wrong with the following setting for DQS tri-state buffer ?

Disable open-drain output.
Open-drain means it will not drive a high, only low or open.

The rest is functional.
The DQ and DM should be the same except for the use-differential.

Disabling the the open-drain may allow the use of a register to drive the OE at the IO buffer.
You can verify your code with my choice here:
https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/75a3d5fe0ef248d7826fdf5fab9c369686c6aa2f/BrianHG_DDR3/BrianHG_DDR3_IO_PORT_ALTERA.sv#L278

Except for parameter 'INVERT_INPUT_CLOCK' as you may be using a separate PLL phase to drive the clock input depending on your design.

[promach]

May I know why you set ENABLE_OE_PORT , INVERT_INPUT_CLOCK , USE_ONE_REG_TO_DRIVE_OE , USE_DDIO_REG_TO_DRIVE_OE , USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY to TRUE ?

[BrianHG]

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/archives/ug-m10-gpio-15.1.pdf

Read page 50.

[BrianHG]

The end result of my parameter selection is a DDR buffer which functions identically to altera Cyclone's altddio_bidir buffer with the following settings:

https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/75a3d5fe0ef248d7826fdf5fab9c369686c6aa2f/BrianHG_DDR3/BrianHG_DDR3_IO_PORT_ALTERA.sv#L390

Now, the 1 piece of code I made will operate identically for Max10 and Cyclone V/IV/III.

[promach]

I do not understand why you use .din( 2'b10 )

[BrianHG]

Since it is a 1 bit DDR buffer, and that is the SDR input -to- DDR data output which will be fed out, a 0 will be sent when the DDR_CLK goes high, and a 1 will be sent when the DDR_CLK goes low.

[promach]

What about inclock and outclock ?

[promach]

Why does a simple tri-state buffer require clock to gate the data signals ?  I suppose it is the job of OE (output enable) signal to do this ?

[promach]

As for the fseek() issue, it seems that row = row_pipeline[0]; contains the XXX value.
But I am not sure what causes this.

Note: According to the simulation waveform, there is no XXX value in any of the DDR command inputs signals

[promach]

I have gotten around the fseek() issue by exporting Vivado simulation libraries to Modelsim.  It seems that it is due to Vivado internal issue, not related to any of the user application coding.

Modelsim waveform using SOFTWARE PLL approach




Modelsim waveform using HARDWARE PLL approach

[promach]

What causes the col address to follow this order : 5, 6, 7, 4, 1, 2, 3, 0 ?

[promach]

For this vcd file, why is the DRAM read operation (709746ns) not reading back the DQ values written at the same address (4096) during DRAM write operation (709578ns) ?

read and write latency = five ck cycles